Please Note: US citizenship or permanent residency is required for this position.

CesiumAstro is a rapidly growing space technology startup in Austin, Texas, developing out-of-the-box communication systems for satellites, UAVs, launch vehicles, and other space and airborne platforms. Our approach is unique, and our team is changing the world of space communications. Learn more about our company at https://www.cesiumastro.com.

The Cesium hardware team is looking for Summer 2022 interns to develop HDL-level FPGA systems for satellite communication systems.

FPGA development interns will work closely with Cesium engineers on FPGA circuits and systems through all phases of the development process. Areas of focus will include design, verification, test, and deployment at the HDL level. FPGA HDL designs will include high-speed serial interfaces and data streams, digital processing cores, multiple clock domains, and management interfaces. Testing, validation, and verification will also be central tasks for any FPGA design. Assignments will be determined by a mix of project availability and the interests of the successful candidates.

Cesium interns regularly present their work to peers, mentors, and Cesium executive leadership throughout the course of the summer. As such, excellent written and verbal communication skills are required.

To apply, please include a cover letter describing your interest in FPGAs and either space systems or communication systems, as well as your status as a US citizen or permanent resident.

CesiumAstro is proud to be an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, protected veteran status, or disability status.
All Cesium internships are compensated competitively and located at our facility in Austin, Texas.

Successful candidates will require, as a minimum:

• Current enrollment in a Bachelor of Science (BS), Master of Science (MS), or PhD program in Electrical Engineering or Computer Engineering from an accredited university.
• Advanced coursework in design, analysis, and implementation of FPGA systems at the HDL level.
• Practical experience designing and building FPGA systems for a research project, competition team, extracurricular activity, or advanced engineering course.
• Experience with FPGA design and verification (Verilog/VHDL, HDL coder, Xilinx’s Vivado, Modelsim, etc.).
• Hands-on experience with lab instruments such as digital oscilloscopes, spectrum analyzers, RF signal generators, and vector signal analyzers.
• Excellent written and verbal communication skills.

Preferred experience includes:

• Experience in digital signal processing.
• Experience with board-level hardware design.
• Advanced coursework in communication systems.