About us:

Mythic has developed a unified hardware and software platform featuring its unique Mythic Analog Compute Engine (Mythic ACE™) to deliver revolutionary power, cost, and performance that shatters digital barriers preventing AI innovation at the edge. The Mythic Analog Matrix Processor (Mythic AMP™) makes it much easier and more affordable to deploy powerful AI solutions, from the data center to the edge device. The company has raised over $165.2 million to date, has over 120 employees, and has offices in Redwood City, CA, and Austin, TX.

About This Role:

Mythic is a fast-paced startup looking for individuals that enjoy broad, flexible roles. The primary responsibility for this position is design for test (DFT) for Mythic's chips. We are looking for someone with exposure to many areas of DFT implementation. You will be working on our state-of-the-art AI accelerator engine. You will be presented with unique DFT architectural and implementation challenges for this new breed of architecture. 

You will contribute in overall DFT architecture planning and implementation. You will get opportunity to work with all industry-leading DFT tools, develop efficient DFT flows, and work with cross-functional teams to promote new DFT architecture.

Here is what you will do:

• As a DFT engineer you will be involved in all aspects of DFT implementation for both SOC and module level design
• IDFT planning, RTL implementation and scheduling.
• MBIST planning and implementation
• iJTAG planning and implementation
• State-of-the-art scan architecture planning and implementation.
• Develop efficient DFT flows and methodology.
• ATPG pattern generation and simulation
• Work with Test Engineering team on patterns handoff and debug.

Here is the background we hope you have:

• 5-7 years of Industry DFT experience. 
• Hands on experience in MBIST planning and RTL implementation
• Experience in JTAG, and iJTAG network implementation.
• Well versed in RTL coding for DFT related logic i.e. clock gates, muxing , Scan Anchors etc. 
• Experience in Scan and ATPG flows.
• Experience in pattern debug on tester.
• Experience in supporting Test Engineering team for faster Silicon bring up.
• Understanding of ICL and PDL flow is a Plus
• Hands on experience with Mentor Tessent Shell based flow is a plus.

The following would be nice to have, but is not required:

• DFT flow development experience is a plus
• Experience with USB and PCIe IP DFT

#LI-Remote 

At Mythic, we pride ourselves in creating a culture where all employees feel valued and appreciated for the diverse perspectives and backgrounds they bring to the team. We aim to hire smart people, give them the resources they need to do their job well, and then leave the rest up to them. We celebrate individual differences and encourage people to be comfortable bringing their authentic selves to work. At the end of the day, we are committed to building a diverse workforce where everyone belongs.

Mythic is an equal opportunity and affirmative action employer. It ensures equal employment opportunity without discrimination or harassment based on race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity or expression, age, disability, national origin, marital or domestic/civil partnership status, genetic information, citizenship status, veteran status, or any other characteristic protected by law.

We look forward to reviewing your application!