Jobs at Ericsson

Lead a cross-functional Silicon CAD technical program portfolio supporting ASIC and FPGA development. Consolidate engineering needs, prioritize initiatives, manage roadmaps, dependencies, milestones, acceptance criteria, qualification, releases, adoption, vendors, and stakeholder alignment. Coordinate design, verification, implementation, infrastructure, security, compliance, and support teams while driving improvements in development quality, productivity, reliability, and predictability.

Leads the portfolio and execution of Silicon CAD initiatives supporting ASIC and FPGA development. Consolidates engineering needs, prioritizes roadmaps, coordinates design and verification dependencies, manages EDA vendor qualification and releases, and drives infrastructure improvements, adoption, documentation, and stakeholder alignment across distributed engineering teams.

Build and improve DevOps infrastructure for hardware validation and ASIC/SoC bring-up. The role focuses on reducing manual setup and configuration drift, improving regression predictability, qualifying tools and releases, enabling scalable experimentation and AI-assisted validation, and providing automation and self-service tooling that increases validation engineer productivity.

Leads Ericsson’s Austin System Virtual Platform team, setting technical direction for SystemC and TLM hardware models, simulation accuracy, performance, CI integration, releases, and supplier deliveries. Acts as an operative product owner, translating stakeholder needs into platform priorities and managing the release train. Collaborates with architecture and software teams while recruiting, developing, and managing the Austin engineering team.

Develop and integrate SystemC/C++ transaction-level models for virtual SoCs and pre-silicon software development. Design test environments, define coverage metrics, perform hardware/software co-simulation and system debugging, and support RTL verification. Collaborate with architects, IP teams, EDA partners, and distributed engineering groups while maintaining simulation infrastructure. The role also involves embedded software, emulation, ASIC development, continuous integration, technical communication, and potentially mentoring other engineers.

Develop and execute automated and regression tests for Ericsson gNodeB and Cloud RAN vDU software. Integrate, troubleshoot, and verify 5G/6G baseband features in laboratory environments; prepare test plans, document results, and analyze feature interactions. Collaborate with design and system engineers while testing wireless protocols, mobility, performance, robustness, configuration, capacity, and RF-related functionality across base stations, mobile devices, and simulators.

Designs and maintains scalable CI/CD pipelines and automation infrastructure for ASIC, SoC, and silicon development workflows. Integrates source control, code review platforms, EDA tools, automated testing, regression management, and quality gates. Improves engineering productivity, infrastructure reliability, resource utilization, and development standardization. Develops dashboards and analytics, and evaluates AI/ML solutions for workflow optimization, failure analysis, regression triage, debugging, and root-cause analysis. Collaborates with design, verification, IT, and infrastructure teams.

Design and verify complex ASIC, SoC, FPGA, and Layer 1 accelerator designs using SystemVerilog and UVM. Build reusable verification environments, drive functional and code coverage closure, validate interfaces and protocols, and debug RTL through post-silicon environments. Develop AI-assisted agentic workflows, CI/CD automation, and machine learning-guided verification processes using Python and related scripting tools. Mentor engineers and collaborate with architecture, RTL, emulation, and system teams.

Lead block- and top-level ASIC/IP verification: architect and build RTL testbenches using SystemVerilog/UVM, develop TLM behavioral models, run hardware emulation/acceleration and SW-driven verification, mentor team members, and define verification strategy and best practices for 5G ASIC IP.

The IP Verification Engineer will lead verification efforts for ASIC IP, build environments, mentor team members, and ensure designs meet specifications in 5G infrastructure.

Leads Ericsson Silicon’s EDA ecosystem strategy and horizontal technical program execution across global engineering teams. Responsibilities include EDA roadmap development, vendor partnerships, tool evaluations, SOW negotiations, license portfolio optimization, capacity planning, budget and total cost analysis, technology-node enablement, and cross-functional alignment. The role drives strategic build-versus-buy decisions, advanced-node flow enablement, AI/ML and cloud EDA adoption, and improvements in tool capability, cost efficiency, and environment readiness.

Design and own microarchitecture and RTL for L1 accelerators, translating DSP/FEC algorithms into high-performance SystemVerilog. Deliver end-to-end IP including specification, RTL, synthesis, timing closure, and hand-off. Lead verification, backend/physical design collaboration, and optimize power/area/throughput across major blocks.

Develop and execute ASIC and IP verification across block and top levels. Build UVM testbenches, TLM models, test plans, and randomized or directed tests; perform RTL debug and coverage closure; and verify hardware with embedded software. The role requires SystemVerilog, UVM, scripting, Linux/Git-based development, and familiarity with interfaces, computer architecture, and relevant semiconductor IP. This is a hybrid, non-remote position in Austin, Texas.

Leads the architecture and evolution of a back-end CAD framework for ASIC physical implementation. Develops advanced-node synthesis, place-and-route, timing closure, power optimization, signoff, automation, and AI-assisted design methodologies. Partners with physical design teams and EDA vendors, evaluates Synopsys and Cadence tools, improves power, performance, area, runtime, and productivity, and mentors engineers.

As a Senior AI Compiler Engineer, you will design and build a custom MLIR-based compiler stack for next-gen silicon, optimizing AI models without an OS. Responsibilities include creating MLIR dialects, ensuring accuracy in lowering computational graphs, and maintaining a high-performance compiler codebase.

Designs, architects, implements, and verifies DFX, DFT, and silicon lifecycle management capabilities across ASIC programs. Responsibilities include DFT planning, production test strategy, in-field testing, telemetry, diagnostics, repair, post-silicon debug, yield bring-up, automation, and collaboration with physical design, test, CAD, EDA, and ASIC partner teams. The role also applies AI to engineering workflows and mentors junior engineers.