Jobs at Ericsson

Designs, verifies, and implements DFX, DFT, and silicon lifecycle management capabilities across ASIC programs from specification through tape-out and field operation. Responsibilities include test strategy, SoC-level DFT planning, in-system testing, telemetry, diagnostics, repair, post-silicon debug, yield bring-up, automation, AI-enabled engineering workflows, and collaboration with physical design, test, EDA, and ASIC partner teams. The role also mentors junior engineers and improves scalable DFX methodologies.

The IP Verification Engineer will lead verification efforts for ASIC IP, build environments, mentor team members, and ensure designs meet specifications in 5G infrastructure.

The Principal AI Model Architect's role includes optimizing model architectures for new hardware, translating AI algorithms into hardware specifications, and projecting performance for silicon design.

Lead block- and top-level ASIC/IP verification: architect and build RTL testbenches using SystemVerilog/UVM, develop TLM behavioral models, run hardware emulation/acceleration and SW-driven verification, mentor team members, and define verification strategy and best practices for 5G ASIC IP.

Define and implement the physical design flow; drive IP and SoC physical design execution; collaborate with CAD and cross-disciplinary teams; mentor and hire engineers; work hands-on with advanced process nodes to achieve PPA, power, and timing signoff.

Design and own microarchitecture and RTL for L1 accelerators, translating DSP/FEC algorithms into high-performance SystemVerilog. Deliver end-to-end IP including specification, RTL, synthesis, timing closure, and hand-off. Lead verification, backend/physical design collaboration, and optimize power/area/throughput across major blocks.

Own operational analytics for Central Engineering, developing KPIs, dashboards, data pipelines, forecasts, scenario models, and executive insights. Analyze headcount, resources, Capex/Opex, budgets, variances, and total cost of ownership to support multi-million-dollar investment decisions. Lead business review cadence, governance, execution tracking, and cross-functional risk resolution while improving reporting processes and operational predictability across engineering sites.

The Principal AI Compiler Engineer designs hardware for AI, ensuring models translate effectively to silicon and perform optimally in 5G applications.

Develop and validate ASIC device drivers and test cases in C/C++ (Zephyr RTOS or Linux kernel), build Python frameworks and automation, assess and visualize test coverage, perform in-lab testing and platform/instrument setup, and collaborate with architects and cross-functional teams to improve validation methodology.

Lead development and strategy for ASIC validation content: design/implement device drivers and test cases in C/C++, evolve validation frameworks, define coverage strategies, lead lab validation and debugging, mentor engineers, coordinate validation workstreams, and drive automation and coverage improvements.

As a Senior AI Compiler Engineer, you will design and build a custom MLIR-based compiler stack for next-gen silicon, optimizing AI models without an OS. Responsibilities include creating MLIR dialects, ensuring accuracy in lowering computational graphs, and maintaining a high-performance compiler codebase.

Leads Ericsson Silicon’s EDA ecosystem strategy and horizontal technical program execution across global engineering teams. Responsibilities include EDA roadmap development, vendor partnerships, tool evaluations, SOW negotiations, license portfolio optimization, capacity planning, budget and total cost analysis, technology-node enablement, and cross-functional alignment. The role drives strategic build-versus-buy decisions, advanced-node flow enablement, AI/ML and cloud EDA adoption, and improvements in tool capability, cost efficiency, and environment readiness.

Owns LSF cluster operations for EDA workloads, including job scheduling, incident troubleshooting, infrastructure automation, and AI-powered developer support tooling. The role serves as the team’s LSF authority, drives measurable efficiency improvements, supports VDI and compute environments, and contributes to AWS cloud integration and infrastructure architecture within Ericsson’s silicon design operations.

The IFM Contract Relationship Manager will manage supplier relationships, oversee contract negotiations, develop strategies, and ensure compliance and governance across regions.