Lead a team of verification engineers ensuring top-level verification of ASIC designs, while collaborating with various teams to enhance processes and strategies.

The ASIC Backend Design Manager will lead a team of backend engineers in driving synthesis and backend functions, ensuring alignment with global priorities and delivering quality silicon for 5G networks.

The Principal AI Model Architect's role includes optimizing model architectures for new hardware, translating AI algorithms into hardware specifications, and projecting performance for silicon design.

The Principal AI Compiler Engineer designs hardware for AI, ensuring models translate effectively to silicon and perform optimally in 5G applications.

As a Senior AI Compiler Engineer, you'll design and implement MLIR-based compilers for 5G/6G silicon, ensuring high precision in hardware-specific IR generation and memory management with a focus on advanced compiler techniques.

Join Ericsson as a Senior RTL Design Engineer to design next-generation L1 accelerators, owning complete microarchitecture from concept to silicon, leveraging SystemVerilog for high-performance hardware.

As an AI Compiler Engineer, you'll optimize 5G/6G workloads, develop MLIR pipelines, and create real-time tools for performance visualization.

The Data Center Engineer is responsible for optical testing, hardware replacement, cabling, troubleshooting, and ensuring optimal data center operations.

As an ASIC Design Engineer, you'll design, verify, and optimize RTL for ASICs in 5G infrastructure while collaborating across teams to meet project goals.

The ASIC Verification Engineer will verify RTL for ASICs, develop test benches, and utilize various modeling and verification techniques for 5G products at Ericsson.

As an ASIC SoC Verification Engineer, you will architect test benches, develop SoC verification plans, and ensure IP component interoperability for 5G/6G products at Ericsson in Austin.

Develop and integrate Transaction Level Models (TLMs) using SystemC/C++, create and debug tests to qualify virtual SoCs, perform HW/SW co-simulation and debug, and provide simulation infrastructure, tooling, and reporting to support hardware and software teams.