Jobs at Microsoft

Lead consultative sales engagements to drive adoption and scaling of AI Workforce solutions (M365 Copilot, Copilot Studio, Copilot Chat, Agents, ME3/ME5, Frontline Worker). Orchestrate virtual teams, develop stakeholder strategies, identify and pursue opportunities, present technical value propositions, and collaborate with internal teams and partners to cross-sell and deliver end-to-end AI workforce transformations.

Lead architecture, development, debug, and deployment of SoC/accelerator firmware libraries (ANC, compute, DMA). Drive silicon bring-up, firmware frameworks, verification, cross-team integration, and mentor engineers while coordinating with hardware, validation, security, and platform teams.

Provides cross-program technical leadership for Microsoft Azure custom silicon virtual platforms. Designs SystemC/TLM models, enables pre-silicon firmware and operating-system development, supports boot and silicon bring-up, and resolves hardware-software integration issues. Defines reusable architecture, simulation and validation practices, and hybrid simulation, emulation, and prototyping strategies. Mentors engineers, influences architecture across organizations, optimizes platform performance, and transitions proven solutions to development teams.

Design and lead firmware architecture and development for server/SoC and rack infrastructure. Drive low-level hardware interfaces, boot and management flows, firmware debug, and delivery of datacenter-class platform technologies.

Leads UX engineering across design and engineering teams, translating research and product concepts into functional prototypes, reusable design systems, front-end solutions, and production-ready code. Drives accessibility, performance, security, and design consistency while influencing product direction, mentoring team members, guiding technical strategy, and collaborating on AI-powered experiences. Owns complex product outcomes, oversees design and code reviews, integrates secure-by-design practices, and supports backlog prioritization and end-to-end product delivery.

Lead design and build of production-ready cloud and AI systems, prioritize security and reliability, ship solutions quickly using modern engineering practices, collaborate with cross-functional teams, mentor engineers, drive customer adoption, and deliver reusable assets and end-to-end complex deliveries.

Design, build, test, and operate production-grade, secure, and scalable software and services. Partner with customers to translate requirements into technical designs, drive engineering best practices (CI/CD, testing, observability), deliver end-to-end solutions, lead technical workstreams, and apply AI/LLM approaches where appropriate to produce production-ready outcomes.

Lead pre-silicon verification for security IP and SoC subsystems: develop C/C++ test content, architect SystemVerilog/UVM environments, drive coverage signoff, mentor engineers, build C test infrastructure and automation (Python/etc.), and accelerate bring-up via FPGA/emulation and hardware debug tooling.

Lead AI silicon architecture direction: define specifications and develop functional/analytical models for AI core compute. Collaborate with software and hardware teams, and guide design, DV, emulation, firmware, and kernel teams through end-to-end silicon development and validation.

Design and develop scalable data solutions and tooling to enable AI and advanced analytics across Azure hardware and software stacks. Identify opportunities for AI-driven impact, build data platforms and visualizations, and collaborate with engineers, data scientists, and program managers to improve efficiency, quality, and operational insights.

Lead supply chain planning transformation for Microsoft Cloud: define strategy, align stakeholders, manage portfolio delivery, coach teams, set KPIs/OKRs, partner with engineering for solutions, oversee change adoption, and ensure solution quality, compliance, and measurable business value across large-scale planning initiatives.

Lead functional verification and validation of complex DPU/SoC designs across pre-silicon and post-silicon stages. Develop UVM/C testbenches, C tests and firmware, define test plans, run regressions, debug failures, create stress/performance scenarios, participate in chip bring-up, and mentor engineers while collaborating with architecture, design, and partner teams.

Lead and execute block- and sub-chip physical design including floorplanning, synthesis, placement, CTS, routing, STA, physical verification, formal equivalency, power/IR-drop/EM analysis. Improve flows, automate methodologies, evaluate technology nodes/IP/EDA tools, report status and risks, and support program needs with occasional travel.

Lead BIOS/UEFI firmware strategy and delivery for Microsoft Azure fleet. Define vendor-agnostic requirements, drive security/validation, oversee NPI for new hardware SKUs, manage agile delivery, and collaborate with partners and silicon vendors to optimize performance, telemetry, and diagnostics.

Lead static timing and physical design validation for digital and mixed-signal blocks, collaborate with RTL/PD/mixed-signal/DFT/CAD teams, run and debug PD flows and timing reports, drive timing closure and PPA trade-offs, and contribute to automation and flow improvements using data-driven mitigations.

Design, verify, and validate analog circuit components for SerDes interface IP (PLL, clock distribution, transmit/receive macros). Perform mixed-signal and post-layout verification, generate timing models, coordinate with layout designers, ensure behavioral model accuracy, and support calibration and post-silicon validation.

Lead functional validation of PCIe IP at block, cluster, or full-chip levels using UVM/C testbenches and VIP. Develop test plans and unit tests, create and manage regression suites, debug failures, and drive fixes. Improve validation efficiency via methodologies and tools and meet coverage goals toward successful tapeout.

Manage global supply planning for Microsoft custom silicon and data center infrastructure. Responsibilities include creating supply plans, coordinating suppliers, 3PLs, and system integrators, reviewing purchase orders, monitoring inventory and shortages, planning product transitions, defining inventory buffers, assessing financial exposure, and performing scenario analysis to mitigate supply risks.

Perform system modeling of analog circuits and SerDes interface IP; coordinate post-silicon interfaces between ATE/validation and design teams; lead debug activities; contribute to analog circuit-level architecture and overall architectural direction; support post-silicon validation, waveform review, and calibration debugging.

Develop and operate large-scale, low-latency Azure cloud services for hardware health monitoring, anomaly prediction, telemetry, reliability, and performance. Evaluate and implement AI technologies, including LLMs, embeddings, RAG, and custom machine learning models, to improve firmware and hardware. Lead root-cause analysis, service restoration, testing automation, security and compliance, production deployment, and analytics reporting.