Jobs at Microsoft

Leads enterprise HDD qualification for Azure-scale deployments, translating requirements into validation strategies and automated test suites. Analyzes failures using traces, logs, telemetry, and diagnostics; partners with suppliers on debugging and corrective actions; drives reliability, security, performance, interoperability, and serviceability improvements. Coordinates cross-functional technical initiatives, advances qualification methodologies, influences industry standards, and mentors engineers.

Develops verification plans, simulation environments, test cases, and coverage strategies for AI silicon IPs, subsystems, and SoCs. Collaborates with architecture, design, and verification teams to debug hardware designs and close functional and code coverage. Preferred experience includes UVM, AXI, embedded processors, secure hardware, FPGA or emulation, RTL, Assembly, linker scripts, and Makefiles.

Own performance verification for fabric interconnect subsystems, covering traffic management, QoS, latency, bandwidth, and congestion. Define verification strategies and signoff criteria with architecture and design teams. Build UVM and formal verification environments, monitors, scoreboards, analytics, and visualization tools. Drive bug discovery, root-cause analysis, coverage, and debug through simulation and assertions. Improve verification automation, apply AI-assisted methods, and mentor engineers.

Lead functional verification and validation of complex DPU/SoC designs across pre-silicon and post-silicon stages. Develop UVM/C testbenches, C tests and firmware, define test plans, run regressions, debug failures, create stress/performance scenarios, participate in chip bring-up, and mentor engineers while collaborating with architecture, design, and partner teams.

Develop and manage hardware decommission demand plans for Microsoft Cloud infrastructure. Collaborate with engineering, finance, customer, data center, and analytics teams to align forecasts, evaluate demand, analyze financial impacts, automate reporting, and provide recommendations supporting strategic decisions.

Design and implement low-power microarchitecture, RTL, IP, and SoC components. Develop UPF power intent, perform synthesis, timing closure, lint, CDC, and quality checks, and collaborate with verification, physical design, performance modeling, and test teams. Write tests and automation scripts, debug designs, deliver qualified hardware blocks, and mentor engineers and interns.

Lead formal verification of fabric interconnect architectures, IPs, subsystems, and reusable components through planning and signoff. Develop verification environments, assertions, abstraction models, checkers, and reusable collateral; perform root-cause analysis using formal analysis, simulation, and debugging; improve productivity through automation and AI-assisted methods; and mentor verification engineers. Collaborate with architecture, design, and verification teams across complex silicon projects.

Perform system modeling of analog circuits and SerDes interface IP; coordinate post-silicon interfaces between ATE/validation and design teams; lead debug activities; contribute to analog circuit-level architecture and overall architectural direction; support post-silicon validation, waveform review, and calibration debugging.

Performs hands-on silicon debug, failure analysis, fault isolation, and yield debugging for Maia and Cobalt silicon programs. Develops debug methodologies, ensures physical and electrical tool readiness, uses ATE and analytical equipment to isolate failures, identifies root causes, and drives corrective actions across design and manufacturing test flows. The role also leads projects, manages external vendors, and coordinates cross-functional teams.

Lead development and delivery of physical design tool flows, methodologies, and sign-off for block, sub-chip, and full-chip levels of Microsoft Next‑Gen AI SoC. Responsibilities include PnR convergence, STA and timing ECOs, PV and FEV sign-off, global clocking, EM/IR analysis, IP collateral validation, design reviews, and mentoring junior engineers.

Execute end-to-end physical design for SoC blocks, from synthesis and RTL through place-and-route and GDS, including clock construction, timing, physical verification, EMIR, formal equivalence, and low-power signoff. Collaborate with CAD, RTL, DFT, architecture, power-performance, technology, and external teams to improve tools, flows, methodologies, PPA, and delivery of production silicon.

Defines technical vision and architecture for agentic engineering across Windows Silicon and System Integration. Leads AI systems from experimentation through production, creating closed-loop workflows for telemetry-driven issue detection, diagnostics, debugging, remediation, and validation. Establishes standards for orchestration, evaluation, observability, reliability, security, privacy, and responsible AI. Influences technical leaders, drives cross-organizational adoption, measures engineering impact, mentors teams, and expands successful agentic capabilities across Microsoft.

Lead performance architecture for AI-focused SoCs and accelerators. Analyze workload bottlenecks, evaluate power and performance trade-offs, develop and integrate SoC and IP models, and collaborate with architects, design teams, and verification engineers to achieve performance goals.

Analyze and optimize GPU and AI workloads across hardware, firmware, drivers, operating systems, APIs, and applications. Investigate performance, power, reliability, telemetry, logs, bugs, and bottlenecks; implement and test Windows OS and feature improvements; collaborate with internal teams and silicon partners; contribute to architecture and design documentation; and develop secure, scalable, compliant code using AI-assisted tools.

Leads end-to-end laboratory support, capacity planning, hardware rack readiness, site launches, expansions, migrations, procurement, and standardized lab operations. Manages schedules, budgets, risks, dependencies, suppliers, documentation, and stakeholder communications across engineering, facilities, finance, security, and vendor teams. Drives global alignment, operational readiness, continuous improvement, and scalable processes for Microsoft cloud hardware infrastructure.

Leads storage hardware qualification and validation for Microsoft Azure data centers. Responsibilities include developing qualification frameworks, reliability and telemetry strategies, debugging complex hardware, firmware, operating system, driver, and cloud-service issues, and coordinating with OEMs, ODMs, and silicon partners. The role drives production readiness, root-cause investigations, automation, technical reviews, and continuous process improvement while providing technical leadership to team members.

Leads end-to-end New Product Introduction readiness for spares serviceability decisions. Manages BOM and FRU processes, coordinates supply chain engineering and manufacturing teams, provides technical program guidance, and represents NPI workstreams in phase reviews and global forums. The role drives cross-functional alignment and decision quality across planning, sourcing, logistics, fulfillment, and hardware supply chain stakeholders.

Lead Microsoft’s commercial cloud demand planning organization for Azure Standard Storage and XArchive. Oversee forecasting, capacity and hardware demand planning, rack deployment, supply optimization, decommissioning, migrations, and capital expenditure planning across 24–36-month horizons. Build and coach technical program management and planning teams, drive data-driven decisions, and collaborate with Engineering, Finance, Hardware, Data Centers, and Supply Chain stakeholders to optimize availability, cost, margins, and customer experience.

Leads multi-generation architecture and delivery of complex network switch hardware for Azure AI infrastructure. Owns requirements, board and system design, validation, manufacturing readiness, supplier execution, and resolution of complex electrical and platform issues. Provides technical authority across ASICs, CPUs, BMCs, high-speed Ethernet, power delivery, signal integrity, telemetry, and management interfaces while driving cross-functional reviews, mentoring engineers, and influencing ODM/OEM partners.

Lead system-level signal and power integrity for high-performance SoCs and platforms. Design, model, and simulate end-to-end power delivery (DC/AC/transient), validate I/O/link performance, and drive PI solutions across silicon, package, board, and platform with cross-functional stakeholders to meet data-center/HPC performance and scaling requirements.