Jobs at Mythic AI

Design, optimize, and verify NVM circuit IP and full-chip simulations for analog compute engines. Develop RNM/functional models (Verilog-A/SystemVerilog/Python), collaborate with validation and backend teams, and support tapeout, silicon debug, and production qualification.

Develop and own DSP and algorithm blocks to mitigate analog impairments for analog compute-in-memory: calibration, non-linearity compensation, offset correction, and error estimation. Build Python frameworks and firmware, improve simulation fidelity, correlate silicon and simulation errors, and lead silicon bring-up, characterization, and productization with cross-functional teams.

Develop and verify designs for AI processors, focusing on system-level verification, testbench development, and collaboration with RTL designers.

Design Verification Engineers will develop and verify designs for AI processors, collaborating across teams to ensure functionality through rigorous testing and innovative strategies.

The Senior Staff Systems Design Engineer will lead the design and development of hardware platforms, ensuring integration between silicon and system design while managing complex PCB designs and collaborating with manufacturing partners.

The RTL Design Engineer will design and implement components for next-gen AI processors, collaborate on microarchitecture, and drive timing closure, optimizing for performance and power efficiency.

Architect and build MLIR ecosystems, extending dialects while ensuring conversion paths. Collaborate with hardware engineers to integrate with PyTorch and modern frameworks.

Develop the next generation AI compiler for Mythic's analog compute, optimizing for dataflow architectures and collaborating with hardware engineers.

Manage complex executive calendars, coordinate travel, handle communications, oversee daily office logistics, and support technology needs.

The role involves verifying mixed-signal and digital systems, creating RNMs, ensuring interface clarity, and contributing to methodologies across teams.

Develop and maintain emulation platforms for AI-centric SoCs, integrate RTL, support firmware bring-up, debug co-design issues, and analyze AI workload performance.

The Compiler Engineer will design compiler IRs and strategies for complex algorithmic workloads, collaborating with hardware engineers to enhance ISA and execution models, ensuring performance and correctness, while simplifying developer experiences.

The Senior RTL Design Engineer will design and implement components for next-generation AI processors, collaborating with various engineering teams to ensure performance and correctness while focusing on low-power, high-performance designs.