Lead the verification strategy and execution for complex SoCs: design UVM and SystemVerilog/C testbenches, integrate SystemC models and FPGA emulation, automate CI/CD with Cadence tools, manage contractors, perform gate-level signoff, and verify PCIe and AMS components.

Lead FPGA development and validation for pre- and post-silicon flows: select/procure prototyping platforms, port ASIC RTL to FPGA, integrate Xilinx IP, implement and validate high-speed interfaces (PCIe), and lead board bring-up and lab debugging for system characterization and automated testing.

Lead development of a compiler toolchain for a custom LLM accelerator: design IR/graph transformations and lowering passes, optimize compute and memory patterns, integrate with PyTorch/JAX/Triton, build test infrastructure, and ensure correctness and performance for hybrid optical-electronic hardware.

Lead the design of processor cores for optical processing units, focusing on advanced architectures, massive parallelism, and efficiency in AI workloads. Collaborate with teams, validate through simulations, and mentor junior architects.

Develop functional and performance models for Neurophos chips using advanced modeling techniques. Collaborate with team to validate hardware models and optimize simulation performance.

Lead the Functional Modeling team to establish infrastructure for software development and RTL validation, utilizing advanced simulation methodologies and mentoring engineers.

The Principal Analog Design Engineer will design high-speed analog circuits and collaborate with teams to optimize performance in photonic AI systems.

Lead the Performance and Power Analysis team to develop modeling infrastructure, define methodologies, and drive architectural decisions for optical computing systems.

Lead the strategic direction and architectural development of the Optical Processing Unit for AI computation, overseeing design, production, and cross-functional collaboration.

Lead the porting and optimization of large machine learning models to Neurophos optical inference engines, ensuring efficient deployment of AI workloads.

Lead embedded firmware development for a novel photonic LLM accelerator: design toolchains and compiler components, optimize compute graphs and memory, integrate with ML frameworks, implement low-level hardware interfaces, and build tests and CI to ensure correctness and high performance of custom hybrid optical-electronic hardware.

The Senior Principal Architect will lead SOC programs, defining architecture, driving performance analysis, and collaborating with teams to realize design intent.