Jobs at NVIDIA

Design and implement an MLIR-based AI compiler for GPU inference: develop graph representations and dialects, optimize performance and memory, define APIs, generate kernels, and collaborate with framework and hardware teams to enable new model patterns and GPU features.

The role focuses on optimizing and managing workload scheduling systems for EDA, enhancing observability, service reliability, and automation while resolving performance issues.

Develop and implement compiler optimization algorithms and code generation for deep learning workloads (XLA/OpenXLA) targeting NVIDIA GPUs. Design graph partitioning and tensor sharding for distributed training/inference, performance tune models, work with ML frameworks (JAX) and hardware teams, and contribute to compiler/tooling (MLIR/LLVM/Triton).

The role focuses on optimizing communication performance for deep learning systems, designing protocols, and collaborating on hardware/software integration while exploring innovative technologies.

Design and implement algorithms and tools for chip-level placement, reshaping, and global routing. Develop computational geometry, placement, routing and graph-optimization solutions, apply machine learning for design space exploration, extend GUIs for debugging/visualization, and collaborate with design teams to deploy high-performance C++ tools impacting next-generation AI chip physical layouts.

The Senior Software Architect will design and implement communication technologies, improve performance for AI and HPC workloads, and lead innovative GPU communication solutions.

The EDA Methodology Architect will define the RTL2GDS flow, collaborate on optimizing designs, analyze performance issues, and drive new methodologies across teams.

Responsible for physical design and implementation of GPUs and ASICs, including methodology establishment, power/clock distribution, and timing closure.

The ASIC Verification Engineer will develop and automate verification test plans, ensuring code coverage and collaborating with teams on design verification processes. This role requires strong analytical and debugging skills with experience in RTL verification methodologies.

Lead development of AI-driven solutions for timing and constraint analysis in EDA, integrating data sources and creating autonomous analysis agents.

You will integrate communication libraries into AI frameworks, analyze workloads, improve AI compilers, and author custom kernels for performance.

The role involves defining architecture for NVLink Fusion, collaborating with customers, mentoring teams, and managing software abstraction layers.

Develop innovative physical design methodologies for GPUs and SOCs, focusing on PPA improvements and collaboration across multiple teams. Use AI/ML to enhance design efficiency.

Develop and debug cloud-native solutions for AI/ML datacenters, focusing on Kubernetes and Slurm enhancements and customer workflows.

Develop optimization engines for VLSI physical design at NVIDIA, focusing on algorithms in C++ for timing optimization, with significant hardware and software collaboration.

Verify SoC and GPU design, architecture and micro-architecture using advanced methodologies. Define verification scope and infrastructure for memory subsystems, verify firmware and hardware/firmware interactions, develop reusable verification components and plans, debug issues, and collaborate with architects, designers, and software engineers across sites.

The role involves designing, building, and deploying compute and networking solutions for AI and HPC, supporting customers with integration and performance debugging.

Lead engineering team to develop AIPerf, an open-source benchmarking tool for LLM inference performance, while overseeing technical direction and mentoring engineers.

Design and implement an LLVM-based backend JIT compiler for NVIDIA GPUs. Develop compiler passes and optimizations, focusing on high performance and low compile time. Collaborate with hardware, compiler, and application teams to resolve issues and influence future GPU architectures.

Lead development and improvement of ASIC integration, build, simulation, CI, and debug infrastructure for high-speed IO GPU IP. Apply automation, metrics, and AI-assisted workflows to improve reliability, turnaround, and debuggability. Collaborate across design, verification, firmware, methodology, and infrastructure teams to root-cause failures and deliver durable process improvements.