Jobs at NVIDIA

Design and develop software solutions for data center servers, focusing on Linux kernel modifications, device drivers, and system optimizations while directly collaborating with Cloud Service Providers.

Leads engineering teams developing platform software for GPU-accelerated applications using Kubernetes, container runtimes, Kata Containers, and Confidential Containers. Responsibilities include enabling GPUs as Kubernetes resources, integrating software across NVIDIA’s technology stack, managing priorities, and delivering secure, reliable distributed systems. The role requires deep systems software expertise, engineering management experience, and hands-on knowledge of containers, Linux, cloud computing, virtualization, and confidential computing technologies.

Lead high-severity incident response and build data pipelines for operational reliability reporting. Analyze incident trends, identify recurring failures and customer-impacting services, and provide prioritized recommendations to engineering leadership. Facilitate postmortems, operational health forums, runbook improvements, and corrective-action tracking. The role requires strong SQL and Python skills, incident-management platform experience, dashboarding expertise, and calm communication during critical incidents.

Design and optimize agentic AI systems for NVIDIA’s CUDA ecosystem, including agent architectures, multi-agent workflows, tool use, memory, orchestration, training, verification, reward, and evaluation systems. Co-design AI systems across models, inference, compilers, runtimes, libraries, kernels, and GPUs. The role requires strong C/C++, Rust, and Python skills, GPU programming expertise, and experience with agent systems, reinforcement learning, or modern AI inference.

Build and operate NVIDIA’s platform infrastructure for EDA and hardware engineering teams. Responsibilities include managing Kubernetes clusters and underlying bare-metal resources, creating self-service infrastructure capabilities, developing controllers and operators, owning CI/CD and shared platform services, onboarding teams and sites, and supporting incident response, reliability, and capacity planning across cloud and physical environments.

Designs and operates scheduling infrastructure for large-scale GPU fleets across Slurm and Kubernetes. Responsibilities include topology-aware placement, fair sharing, quotas, preemption, reservations, backfill, workflow orchestration, reliability, and performance measurement. The role requires production systems ownership, on-call support, open-source contributions, and collaboration with platform, storage, networking, and AI research teams.

Design and build NVIDIA’s AI data platform for multi-cloud GPU fleets. Responsibilities include high-throughput data paths, distributed caching, checkpoint management, Kubernetes-native storage integrations, quota and lifecycle systems, I/O telemetry, capacity forecasting, and production reliability. The role partners with AI researchers and supports workloads across Kubernetes and Slurm, requiring expertise in distributed storage, data infrastructure, I/O performance, and systems programming.

Architect next-generation CPU and SoC system software in collaboration with hardware, software, ASIC, verification, platform, customer, and industry teams. Influence hardware architecture decisions through expertise in software architecture, operating systems, drivers, and C development. Provide technical direction, customize solutions for partners, research industry trends, and advise senior management on CPU and SoC architecture strategies.

Lead end-to-end GPU and systems performance engineering for NVIDIA CSP and hyperscale customers. Drive workload characterization, profiling, benchmarking, regression analysis, tooling validation, and optimization across CUDA, NCCL, drivers, firmware, and distributed ML infrastructure. Translate customer performance gaps into engineering priorities, influence multiple teams, and ensure performance validation is ready for deployments and acceptance testing.

Design and operate large-scale infrastructure supporting GPU- and CPU-based EDA workloads. Build automation for provisioning, configuration, deployment, lifecycle management, monitoring, health remediation, cluster enrollment, and recovery across Linux compute fleets. Integrate services with schedulers, infrastructure systems, and observability platforms. Participate in incident response, root-cause analysis, capacity planning, and reliability improvements while collaborating with EDA, networking, storage, and hardware teams.

Provide first-line support and troubleshooting for an HPC environment, monitor system health, triage incidents, perform maintenance and patching, and produce runbooks and documentation. Improve processes and escalate to SMEs for complex issues while supporting scheduling, compute, storage, and access concerns.

Architect and deliver Reliability, Availability, and Serviceability hardware features for advanced CPUs and SoCs. Responsibilities span architecture definition, RTL implementation support, verification planning, silicon validation, fault injection, debug, production readiness, error recovery, telemetry, containment, and serviceability. The role collaborates with design, verification, firmware, software, and platform teams, and applies resiliency principles to high-reliability and radiation-aware environments.

The role involves developing and implementing features for the CUDA driver and collaborating on solutions for NVIDIA's compute platform, requiring strong coding and design skills.

Drive static timing analysis and closure for DFT logic across NVIDIA GPUs, CPUs, DPUs, LPUs, and SoCs. Develop timing constraints, resolve timing paths through ECOs, drive timing and power convergence, and improve automation and workflow standardization. Collaborate with physical design, DFX, clock, and other engineering teams across block, cluster, and full-chip levels.

Lead the design and development of high-performance AI networking software for NVIDIA BlueField DPU and ConnectX products. Manage hyperscaler technical engagements involving coding, system bring-up, performance tuning, failure analysis, and production hardening. Collaborate across engineering, product, architecture, and customer teams to translate needs into product features and roadmap improvements. Drive reliability, performance, debuggability, and tooling enhancements across firmware, drivers, operating systems, and applications.

Leads post-silicon enablement of design-for-test capabilities from silicon bring-up through production. Analyzes test data, quality, yield, efficiency, and failures; influences DFT architecture; develops validation, debug, deployment, and documentation methodologies; and supports test-time and power optimization. Collaborates with design, product, and test teams to connect pre-silicon decisions with production outcomes for advanced semiconductor devices.

Architects and builds scalable agentic AI systems spanning runtimes, inference, evaluation, orchestration, distributed execution, ETL, HPC, cloud, Kubernetes, and GPU environments. The role optimizes reliability, performance, scalability, resource utilization, and developer experience; prototypes emerging technologies; writes production software; and provides technical leadership across research, engineering, product, and infrastructure teams.

Design and architect on-chip GPU/CPU clock domains, collaborate with front-end, physical design, timing, verification and SW teams to implement clock RTL, optimize PPA, support ASIC implementation through sign-off and silicon bring-up.

Work with ASIC Infrastructure to enhance design productivity, deploy AI toolsets at scale, and improve CI systems while solving complex issues.

Lead CPU performance verification strategy, test planning, stimulus and microbenchmark development, regression debugging, coverage closure, and performance correlation tooling. Collaborate with architects and design engineers on CPU microarchitectural features, guide junior engineers, and support validation across CPU designs. Requires CPU microarchitecture knowledge, workload analysis, Perl or Python scripting, C/C++ proficiency, and 12+ years of experience. ARM A64 and x86 experience are preferred.