Jobs at SiFive

Lead the design and implementation of debug, trace, and profiling hardware within SiFive's RISC-V ecosystem, focusing on quick market delivery and high performance.

Define end-to-end formal verification strategies for complex SoCs and IP subsystems. Identify high-risk architectural issues, develop formal methodologies, manage abstractions, drive proof convergence, and improve implementations for correct-by-construction designs. Lead verification across large hardware systems, including CPU microarchitecture, communication fabrics, and protocols, using formal methods and simulation co-verification.

Analyzes and optimizes SiFive IP power consumption across architecture, logic, circuit, RTL, and silicon levels. The role develops power models, correlates them with RTL and silicon results, guides performance-power tradeoffs for high-performance out-of-order CPUs, and improves power analysis workflows. Candidates need advanced computer architecture education, 5+ years of power benchmarking and ASIC optimization experience, and strong problem-solving skills.

Own verification planning, execution, debugging, coverage closure, and methodology for high-performance out-of-order RISC-V CPU core components. Develop SystemVerilog and UVM environments, assertions, scoreboards, stimulus, and coverage models. Partner with architecture and RTL teams to identify risks, resolve microarchitectural issues, and achieve signoff quality across frontend, midcore, load-store, execution, vector, and hardware prefetch units. Mentor engineers and improve verification infrastructure and practices across future CPU generations.

Own functional verification for high-performance out-of-order RISC-V CPU core units from block level through core integration. Develop test plans, UVM environments, testbenches, checkers, scoreboards, assertions, constrained-random tests, and coverage models. Debug failures, identify RTL and verification issues, close coverage gaps, and collaborate with architecture, design, performance, and software teams. Contribute reusable verification infrastructure and methodology for future CPU generations.

Staff Design Verification Engineer responsible for planning and executing verification for high-performance out-of-order RISC-V CPU cores, including vector functionality and microarchitectural interactions. Develops verification environments, checkers, scoreboards, assertions, stimulus, and coverage models; leads debug and coverage closure; partners with architecture and design teams; improves verification methodology; and mentors engineers.

Own formal verification for high-performance out-of-order RISC-V CPU cores, including planning, assertions, proof strategies, abstraction, debugging, and signoff closure. Develop scalable formal environments and infrastructure for control, ordering, pipeline, load-store, clock-gating, and microarchitectural behavior. Analyze failures and coverage gaps, collaborate with architecture and RTL teams, improve verification methodology, and mentor engineers.

Staff Design Verification Engineer responsible for verifying high-performance out-of-order RISC-V CPU core functionality, especially ALU and integer execution pipelines. Owns verification planning, test development, debug, coverage closure, assertions, scoreboards, and signoff from block through core integration. Partners with architecture and RTL teams to identify microarchitectural risks and improve design quality. The role also contributes reusable automation and methodology while mentoring verification engineers.

Own formal verification for high-performance out-of-order CPU core units from planning through signoff. Develop assertions, properties, harnesses, proof infrastructure, and abstraction strategies; analyze counterexamples, vacuity, over-constraints, and proof failures; and verify pipeline control, ordering, hazards, forward progress, and clock gating. Collaborate with architecture, RTL, and simulation DV teams, improve formal methodology and automation, and mentor engineers.

Own verification of high-performance out-of-order RISC-V CPU cores, with emphasis on vector functionality and microarchitecture. Develop verification plans, environments, checkers, scoreboards, assertions, constrained-random and directed tests, and coverage models. Debug RTL and infrastructure failures, verify RVV behavior and scalar-vector interactions, close coverage gaps, and collaborate with architecture, design, performance, and software teams to achieve signoff quality.

Own formal verification of high-performance out-of-order RISC-V CPU cores from planning through signoff. Develop assertions, properties, checkers, harnesses, abstractions, and proof infrastructure; analyze failures and counterexamples; verify pipeline control, issue and commit logic, load-store ordering, hazards, forward progress, and clock gating. Collaborate with architecture, RTL, and simulation DV teams, improve formal methodology, and mentor engineers.

Lead verification for a cache-coherent interconnect subsystem based on ARM CHI. Develop verification environments, protocol checkers, scoreboards, assertions, coverage models, and constrained-random tests covering coherency, ordering, flow control, retries, and integration. Analyze failures across specifications, RTL, and testbenches; drive verification strategy, coverage closure, methodology improvements, and durable fixes. Collaborate with architecture, design, formal, and software teams while mentoring engineers and supporting signoff.

Develop and maintain SiFive’s verification platform infrastructure, libraries, tools, and methodologies for design verification. Build functionality using Chisel and CIRCT, create Scala-based verification libraries and generators, and develop Python tools for querying design intent and metadata. Collaborate with platform technology teams, support end-to-end verification flows, and educate teams on best practices. The role requires compiled and scripting language experience, modern software engineering knowledge, and experience deploying production software.

Develops and deploys power analysis flows, models, and measurement infrastructure for SiFive processor IP. The role correlates power models with RTL and silicon, supports architecture exploration, and optimizes ASIC power across architecture, logic, and circuit levels. It requires advanced computer architecture knowledge, particularly high-performance out-of-order CPUs, along with software engineering practices for maintaining large object-oriented codebases.

Analyze and benchmark SiFive IP power consumption, correlate power models with RTL and silicon, work with architects and designers to optimize power/performance trade-offs, and innovate improvements to power analysis flows.

The role involves analyzing and optimizing power consumption in SiFive IP, guiding architecture for power efficiency, and improving power analysis flows.

Develop and deploy methodologies for measuring and analyzing power consumption of SiFive IPs. Guide teams in designing energy-efficient IPs through power modeling and analysis.

Design and implement CPU power management, reset, and clocking solutions. Collaborate with teams to verify and optimize designs based on RISC-V architecture.

Lead verification for a scalable cache-coherent interconnect subsystem: define strategy and test plans, build verification environments, checkers, assertions and coverage, verify CHI/ACE/CXL/AXI flows, create constrained-random and directed tests, debug across RTL/formal/software, and drive methodology and mentorship to improve verification quality and closure.

Lead verification for a scalable cache-coherent interconnect subsystem. Define strategy, develop environments, checkers, assertions and coverage, verify CHI/ACE/CXL/AXI flows, debug root causes, partner with architecture/RTL/formal teams, and mentor engineers to improve verification quality and signoff.