Jobs at SiFive

Develop and maintain core tools for microprocessor design, including simulation and build tools. Requires systems-level programming and tool validation experience.

Design interconnect IP, architect TileLink interconnect, enhance performance, integrate into SiFive's framework, perform verification, and maintain documentation.

Lead a performance engineering team to research and develop high-performance processor architectures, defining targets and guiding implementation in RTL, while analyzing performance bottlenecks.

Design and implement debug, trace, and profiling hardware, collaborate with cross-functional teams, and lead improvements in hardware design processes.

Design and implement TileLink interconnects, cache controllers, protocol bridges and other uncore logic as configurable RTL generators (Chisel). Integrate designs into SiFive's Chisel/FIRRTL framework, enable automatic configuration, verification, and documentation, and collaborate with verification teams and peers to deliver high-performance, configurable interconnect IP.

The role involves analyzing and optimizing power consumption in SiFive IP, guiding architecture for power efficiency, and improving power analysis flows.

Develop and deploy methodologies for measuring and analyzing power consumption of SiFive IPs. Guide teams in designing energy-efficient IPs through power modeling and analysis.

Lead the design and implementation of debug, trace, and profiling hardware within SiFive's RISC-V ecosystem, focusing on quick market delivery and high performance.

Lead verification strategy and execution for CPU frontend in high-performance out-of-order cores. Define test plans, checkers, assertions, coverage, and stimulus for branch prediction, instruction fetch, redirects, recovery, and MMU/ITLB interactions. Partner with architects, RTL, performance, and verification teams, apply simulation, formal, and emulation methods, drive block- and core-level signoff, mentor engineers, and build reusable DV infrastructure and methodology.

Lead verification strategy and execution for CPU-subsystem power-management across unit, subsystem, and signoff levels. Define tests, assertions, coverage, and corner-case stress scenarios for DVFS, retention, clock/reset sequencing, power gating, and multi-domain interactions. Drive debug, root-cause analysis, formal and power-aware methods, reusable infrastructure, and mentor engineers to achieve data-center-grade signoff readiness.

Lead verification strategy and execution for advanced hardware prefetch in high-performance out-of-order CPU cores. Define test plans, checkers, assertions, coverage, and stimulus to validate prefetch training, stream management, request generation, DCache interactions, CSR configurability, and corner cases. Collaborate with architects, RTL, performance, and software teams; apply simulation, formal, emulation, and performance validation; drive debug, coverage closure, and mentor engineering teams to raise DV quality and reusable methodology.

Lead verification strategy and execution for a cache-coherent interconnect subsystem, defining plans, assertions, checkers, scoreboards, and coverage. Develop directed and constrained-random scenarios, drive cross-team verification across interfaces and bridges, apply simulation/formal/emulation as appropriate, perform root-cause analysis, and mentor engineers to raise verification quality and reusable infrastructure for high-performance CPU/SoC platforms.

The Verification Architect at SiFive will ensure design fidelity for RISC-V based CPUs, develop verification strategies, and improve quality through collaboration with design teams.

Design and microarchitect power-management, reset, and clocking subsystems for high-performance CPU and SoC IP. Specify architectures, implement RTL, perform sandbox verification, collaborate with verification, physical implementation, and software teams to meet frequency, area, and power goals.

Design and microarchitect power management, clocking, and reset solutions for RISC-V CPU and SoC IP. Define requirements, implement RTL, collaborate on verification, physical implementation, and software enablement to meet frequency, area, and power goals.

Design and implement configurable TileLink interconnects, cache controllers, protocol bridges and other uncore infrastructure as RTL generators in Chisel. Integrate with SiFive's Chisel/FIRRTL framework, perform initial sandbox verification, collaborate with verification teams on test plans, document designs, and improve generator tooling for automatic configuration, verification, and packaging.

Design and microarchitect power-management, reset, and clocking solutions for high-performance CPU and SoC IP. Develop RTL, spec microarchitecture, run sandbox verification, collaborate with verification, physical implementation, and software teams to optimize frequency, area, and power and drive designs through tapeout.

The Staff Design Verification Engineer drives the verification of cache-coherent interconnect subsystems, focusing on CXL protocols and integration, defining verification plans, and improving overall verification quality through collaboration and mentorship.

The intern will join the Design Verification Infrastructure team to develop and maintain the Verification Platform, enhancing design verification technologies through collaboration and software development in Scala and Python.

The Principal Design Verification Engineer will lead verification strategies, execute high-performance CPU subsystem verification, and improve methodologies, with a focus on CPU core and coherent interconnect verification.