Jobs at SiFive

Design and implement CPU microarchitecture features and ISA extensions using Chisel. Integrate designs into Chisel/FIRRTL framework, perform sandbox verification, collaborate on verification plans, optimize for physical implementation and performance, and document microarchitecture specifications.

Design and implement CPU power management, reset, and clocking solutions. Collaborate with teams to verify and optimize designs based on RISC-V architecture.

The Verification Engineer ensures the accuracy of highly configurable cores and other IPs through state-of-the-art methodologies, test planning, execution, and quality assurance.

Develop and maintain core tools for microprocessor design, including simulation and build tools. Requires systems-level programming and tool validation experience.

Design interconnect IP, architect TileLink interconnect, enhance performance, integrate into SiFive's framework, perform verification, and maintain documentation.

Lead a performance engineering team to research and develop high-performance processor architectures, defining targets and guiding implementation in RTL, while analyzing performance bottlenecks.

Design and implement debug, trace, and profiling hardware, collaborate with cross-functional teams, and lead improvements in hardware design processes.

Lead the development of SiFive BSPs, creating roadmaps and supporting Yocto-based distributions for various platforms, collaborating with teams and ensuring best open source practices.

Lead the architecture and design of energy-efficient processors, analyze power consumption, and develop models and flows for optimization.

The Verification Architect at SiFive will ensure design fidelity for RISC-V based CPUs, develop verification strategies, and improve quality through collaboration with design teams.

The role involves analyzing and optimizing power consumption in SiFive IP, guiding architecture for power efficiency, and improving power analysis flows.

Develop and deploy methodologies for measuring and analyzing power consumption of SiFive IPs. Guide teams in designing energy-efficient IPs through power modeling and analysis.

Design and implement TileLink interconnects, cache controllers, protocol bridges and other uncore logic as configurable RTL generators (Chisel). Integrate designs into SiFive's Chisel/FIRRTL framework, enable automatic configuration, verification, and documentation, and collaborate with verification teams and peers to deliver high-performance, configurable interconnect IP.

Lead the design and implementation of debug, trace, and profiling hardware within SiFive's RISC-V ecosystem, focusing on quick market delivery and high performance.

The intern will join the Design Verification Infrastructure team to develop and maintain the Verification Platform, enhancing design verification technologies through collaboration and software development in Scala and Python.

The Staff Design Verification Engineer drives the verification of cache-coherent interconnect subsystems, focusing on CXL protocols and integration, defining verification plans, and improving overall verification quality through collaboration and mentorship.

The Principal Design Verification Engineer will lead verification strategies, execute high-performance CPU subsystem verification, and improve methodologies, with a focus on CPU core and coherent interconnect verification.

The Staff Design Verification Engineer will lead verification for a cache-coherent interconnect subsystem, focusing on verification planning, execution, and improving methodologies. Key responsibilities include developing robust verification environments and addressing complex verification problems.

As a Datacenter System Software Architect at SiFive, you'll design RISC-V Linux systems for datacenters, engage with customers, and optimize performance across software and hardware.