Jobs at SpaceX

Develop next-gen ASICs for space deployment, perform design implementation, collaborate with teams, and resolve timing/congestion issues in chip development.

Develop next-generation silicon for SpaceX's Starlink initiative, performing physical implementation steps, improving methodologies, and collaborating with design teams.

The engineer will handle full-chip physical verification, including DRC, LVS, and ESD signoff, while optimizing design flows for advanced SoCs and engaging with foundry teams.

Lead global sourcing and supplier management for datacenter memory and storage (HBM, DDR5, SSDs). Define commodity strategy and roadmaps, secure large-scale supply, negotiate high-value agreements, manage inventory and risk, drive cost reductions, and track KPIs while partnering with engineering and platform teams.

Lead digital ASIC verification at block and system level: write and execute test plans, develop test harnesses and regressions, close coverage, support pre-silicon verification, chip bring-up and post-silicon validation, and collaborate with cross-disciplinary teams to verify complex digital designs.

Develop and execute digital ASIC verification at block and system level. Build SystemVerilog (UVM and non-UVM) testbenches, write test plans, run regressions, close coverage, automate test generation with Python and MATLAB, and support pre-silicon verification through post-silicon validation and chip bring-up.

Develop and verify Design for Test (DFT) infrastructure for ASIC/SoC designs: evaluate scan insertion readiness, integrate and verify DFT IP, run ATPG and gate-level simulations, create post-silicon ATPG content, and collaborate with physical design and manufacturing teams to ensure high scan coverage and testability in silicon.

The Principal Design Verification Engineer will verify ASICs/FPGA designs, lead test plans, and ensure designs meet specifications. Collaborating with cross-disciplinary teams, the role involves pre-silicon verification and post-silicon validation.

The Sr. IC Package Design Engineer will lead advanced package selection for ASICs, manage design verification, and collaborate with cross-functional teams for optimal silicon integration.

Manage end-to-end strategic relationships with ODMs and CMs for hardware builds, optimize processes, negotiate agreements, and drive quality and cost efficiencies.

The Global Supply Manager will oversee sourcing strategy and supplier management for GPUs and AI accelerators, ensuring timely delivery and performance management, and driving innovation in procurement within a high-paced tech environment.

The Global Supply Manager will manage sourcing strategies for datacenter switches and optics, negotiate supplier agreements, optimize costs, and ensure supply chain resilience.

The Global Supply Manager will define natural gas supply strategy, manage pipeline infrastructure, negotiate contracts, and ensure cost-effective gas delivery for SpaceX's power plants.

Lead development and optimization of DFT architectures for ASICs using Tessent and ATPG methodologies. Own scan insertion, compression, memory/logic BIST, hierarchical test flows, gate-level simulation debugging, post-silicon validation, and DFT IP integration. Automate test processes and analyze data with scripting languages. Support design readiness checks and collaborate across systems, firmware, architecture, and validation teams toward tapeout and product deployment.

Own end-to-end strategic management of ODMs and CMs for datacenter compute and network hardware (L10/L11). Define build strategies and SOWs, drive cost reduction, lead supplier selection/qualification/onboarding, standardize NPI-to-mass-production, implement inventory/WIP optimization, and enforce KPIs for cost, quality, speed, yield, and resilience while supporting aggressive global cluster deployment.

Lead and grow a sourcing team responsible for GPU/CPU/storage/server/rack procurement and ODM/CM relationships. Define commodity strategies and roadmaps, secure supplier capacity, negotiate agreements, manage supply risk and cost through should-cost/value engineering, track KPIs, and align cross-functionally to support large-scale AI training infrastructure.

Lead and grow a sourcing team for datacenter compute infrastructure supporting SpaceXAI. Define commodity strategies and roadmaps, secure GPU/CPU/storage supply, manage ODM/CM relationships, negotiate major agreements, mitigate supply chain risks, drive cost reduction, align with engineering, and report KPIs to senior leadership.

Lead cross-disciplinary teams to drive complex ASIC projects from kickoff through production. Manage schedules, suppliers, bring-up, qualification, and ramp-to-production while coordinating with internal and external partners to resolve issues and accelerate silicon deployment.

Develop and optimize DFT architectures for ASICs, performing validation, integration, and test pattern generation, while collaborating with cross-functional teams.

Design, implement, and maintain AV systems for collaboration and event spaces. Collaborate with construction and design teams, support high-profile events (launches, concerts), and provide technical AV, lighting, and automation support and troubleshooting.