Top Engineering Jobs in Austin, TX

The Staff DevOps Engineer will enhance the engineering experience at Arm, overseeing technical deliveries and collaborating with teams to improve software and hardware tooling through cloud services and CI/CD practices.

Design and define high-speed on-chip interconnect architectures (coherent and non-coherent) including PCIe, CXL, and UA Link for scalable SoCs. Lead roadmap and early customer architecture engagements, collaborate with performance, power, physical design, software and firmware teams, and perform workload analysis and performance modeling to meet compute, memory, and interconnect targets.

Define and evaluate next-generation CPU microarchitectures for Cortex-X and Neoverse, develop performance models and simulations, analyze workloads, estimate performance/power/area trade-offs, collaborate with design teams and partners, and mentor junior engineers.

Customer-facing technical lead for platform firmware bring-up and debug across silicon, firmware, and OS layers. Support reference and custom platforms, debug DDR/PCIe and multi-socket issues, drive triage and root-cause analysis with internal teams, deliver workshops and documentation, and enable partners to accelerate platform readiness.

Manage and advance internal server lab and compute infrastructure: hardware board bring-up, lab IT and networking, CI/CD (GitLab) reliability, provisioning automation, MAAS administration, backup/recovery, co-lo logistics, cloud zone maintenance, security escalations, procurement coordination, documentation, and platform enablement support.

Lead end-to-end ATE secure provisioning for semiconductor manufacturing: define and implement fuse programming and lifecycle transitions, develop/validate Advantest 93K test methods, ensure secure boot and device identity, coordinate with Design/DV/Firmware/Security/Manufacturing, and define production controls, traceability, and guardrails across wafer sort, final test, SLT, and HVM.

As a SoC Emulation Engineer, you'll develop verification testbenches, modify RTL for SoC, and collaborate to define future architectures.

As a Performance Analysis Engineer, you will analyze SoC performance, identify bottlenecks, collaborate with architects, and develop testing workflows.

Design RTL logic for a coherent interconnect fabric using SystemVerilog. Collaborate with verification, implementation, performance, and power teams to deliver high-performance, low-power IP. Track and coordinate tasks, debug functional and performance issues with simulation and tools, and improve design methodology across the System IP group.

Lead architecture, design, and delivery of coherent and non-coherent SoC interconnect fabrics. Define topology, QoS, latency, bandwidth, and power strategies; drive performance modeling, RTL microarchitecture and verification, debug system-level issues, mentor engineers, and plan interconnect roadmaps while collaborating with CPU/GPU/NPU/memory teams.