Top Engineering Jobs in Austin, TX

Develops micro-architecture and RTL for SoC power management, voltage control, clock, and reset IP. Designs power-state transitions and multi-domain control logic while meeting functional, power, performance, area, and timing goals. Performs synthesis, timing analysis, lint, CDC, RDC, and power-aware checks; collaborates with verification and implementation teams on integration and debugging. Contributes to design methodologies, automation, technical reviews, and delivery of semiconductor projects.

Lead cross-functional product engineering for SoC/CPU/GPU manufacturability from pre-silicon readiness through post-silicon bring-up. Own manufacturing flow, ATE/SLT test and correlation, yield improvement, silicon/package reliability qualification, PVTF characterization, and failure analysis while coordinating with foundries, OSATs, design, validation, test, and quality. Support NPI/HVM readiness and audits, with international travel up to 20%.

Build and operate server lab, data center, networking, cloud, and compute infrastructure for server development and validation. Responsibilities include hardware deployment, racking and cabling, Linux administration, networking, CI/CD runner and pipeline management, validation testing, log analysis, backups, recovery, security, incident response, troubleshooting, documentation, and user support. The role is primarily onsite in Austin with occasional travel to offsite colocation facilities.

Develop verification plans, SystemVerilog/UVM testbenches, constrained-random stimulus, coverage, and regression strategies for Arm's coherent interconnect products. Collaborate with architects and designers to debug features, resolve functional failures, close coverage, and improve verification methodologies. The role requires CPU microarchitecture expertise, including cache coherence, memory systems, and AMBA bus protocols.

Develop and operate software infrastructure supporting Arm CPU design and verification. Build automation for distributed HPC workloads, CI and regression systems, observability, source-control and verification-tool integrations. Diagnose complex issues across software, hardware verification, operating systems, compute, and storage. Improve compute utilization, verification throughput, failure analysis, and engineering workflows while delivering maintainable production-quality software.

Provides independent quality oversight for CPU development across requirements, design, verification, release, and maintenance. Leads quality reviews, defect investigations, root-cause analysis, corrective actions, and errata resolution. Uses quality data and customer feedback to identify trends, improve verification effectiveness, strengthen engineering practices, and simplify development processes. Collaborates with engineering teams and contributes to review boards and cross-team improvement initiatives.

Leads pre-silicon quality engineering for high-speed I/O subsystems including DDR, PCIe, eUSB, and SerDes. Drives DFX metric closure, validates silicon-to-simulation correlation, analyzes eye diagrams, BER, margining, and BIST data, and develops test automation and visualization scripts. Chairs TPIP councils and collaborates with vendors, architects, integration, validation, package, and SIPI teams to ensure quality across upcoming systems-on-chip.

Develop and maintain SystemVerilog/UVM verification environments for Memory Controller IP. Create verification plans, tests, assertions, coverage models, and scoreboards for LPDDR and DDR technologies. Analyze regressions, simulations, waveforms, and logs to debug RTL, testbench, and protocol issues. Collaborate with architects, RTL designers, and verification teams to achieve coverage closure and sign-off, while improving automation and verification workflows.

Architect high-speed PCIe, CXL, and UA Link interconnect subsystems for scalable Arm-based SoCs. Define technology roadmaps, develop implementation-ready specifications, integrate coherent and non-coherent architectures, and optimize bandwidth, latency, power, and performance. Collaborate with customers and multidisciplinary hardware, software, firmware, physical design, and platform teams while guiding workload analysis, performance modeling, and end-to-end system solutions.

Owns secure semiconductor manufacturing test and provisioning on Advantest 93K ATE. Responsibilities include test architecture, SmarTest program development, first-silicon bring-up, characterization, HSIO and structural test integration, hardware coordination, silicon and ATE debug, production release, OSAT deployment, yield improvement, and high-volume manufacturing readiness.