Top Engineering Jobs in Austin, TX

Owns component engineering strategy and lifecycle risk management for board-level electronics from architecture and NPI through production and end of life. Responsibilities include component selection, characterization, qualification, alternate-source development, BOM risk analysis, dual-sourcing, obsolescence mitigation, supplier collaboration, reliability support, and component governance. The role partners with Electrical Engineering, Supply Chain, Manufacturing, Quality, suppliers, and contract manufacturers to balance technical performance, reliability, cost, availability, and lifecycle risk.

Conduct original robotics research across areas such as robot learning, perception, planning, control, safety, systems, and mechatronics. Develop and implement novel methods on real robots and in simulation, integrate capabilities into intelligent systems, publish research, identify system-level requirements, and collaborate with multidisciplinary researchers and external partners to shape Arm’s robotics technology roadmap.

Conduct original robotics research across learning, perception, planning, control, safety, systems, and mechatronics. Develop and evaluate methods on real robotic platforms and simulations, integrate multidisciplinary capabilities into intelligent systems, publish research, identify system-level bottlenecks, and influence the technical roadmap for future robotics compute and software platforms.

Build and operate scalable platform services and APIs that improve engineering workflows. Develop Kubernetes operators, automate self-service capabilities, provision cloud infrastructure with Terraform, and manage reliable workloads using AWS, Docker, Kubernetes, Helm, and ArgoCD. Lead technical initiatives, apply secure software engineering practices, support production systems, and participate in an on-call rotation while collaborating across engineering teams.

Design and integrate complex compute subsystems and SoCs, including PCIe, DDR, HBM, UCIe, and Ethernet IP. Develop micro-architecture specifications and RTL, perform design checks, debug issues, and collaborate with verification, performance, backend implementation, and project management teams. Support floor planning, timing closure, design methodologies, and team development while guiding other engineers.

Provide technical mentorship and support to partners integrating Arm CPUs and System IP into SoCs. Perform RTL simulation-based debugging, SoC build reviews, deliver training, influence IP development, test IP, and create knowledge-base content and tooling to improve partner outcomes.

Design and implement SystemVerilog RTL for memory controller functional units. Develop specifications and microarchitecture, collaborate with design and verification teams, debug functional and performance issues, and meet performance, power, and area targets. The role requires knowledge of DRAM standards, AMBA bus protocols, RTL design, synthesis, and design-quality checks such as lint and CDC analysis.

Develop and deploy Raven, a C++ dynamic random test generator for Arm CPU verification. Responsibilities include implementing verification functionality, creating test templates for architectural and microarchitectural features, debugging user and QA issues, collaborating with CPU verification engineers, and applying computer architecture specifications. The role requires strong C++ development, assembly programming, computer architecture knowledge, and familiarity with CPU verification environments.

Develop cycle-accurate performance models for coherent and non-coherent Arm interconnects. Collaborate with micro-architects, RTL, validation teams, and customers to assess architectural trade-offs, develop features, build performance test suites, identify bottlenecks, and deliver data-driven system performance insights. The role requires strong C++, SystemC TLM, and Python skills, plus expertise in SoC performance modeling and computer architecture.

Design RTL logic for a coherent interconnect fabric using SystemVerilog. Collaborate with verification, implementation, performance, and power teams to deliver high-performance, low-power IP. Track and coordinate tasks, debug functional and performance issues with simulation and tools, and improve design methodology across the System IP group.