Top Engineering Jobs in Austin, TX

Develop and analyze memory controller IP and system performance models for Arm-based SoCs. Optimize power, performance, and microarchitecture using workload analysis, simulation, and emulation. Create performance methodologies, identify system bottlenecks, guide internal teams and partners, correlate models with RTL, and mentor engineers. Requires strong computer architecture expertise, C++ development, scripting, and experience with memory or interconnect performance modeling.

Own end-to-end technical delivery for Arm’s engineering platforms, including requirements, planning, implementation, production support, and on-call incident response. Develop and maintain CI/CD, build, testing, cloud, containerization, infrastructure-as-code, and clustered computing solutions. Improve developer experience through automation, self-service infrastructure, and efficient engineering workflows.

Leads end-to-end product engineering for advanced HPC silicon from pre-silicon readiness through bring-up, qualification, production ramp, and HVM. Owns silicon characterization, performance and power correlation, HSIO validation, manufacturing test, SLT, yield, reliability, failure analysis, and advanced packaging. Partners cross-functionally on productization requirements, risk mitigation, manufacturing readiness, and root-cause resolution. Provides technical leadership, communicates complex issues, establishes product-health metrics, and mentors engineers.

Design and integrate PCIe, CXL, and other IP subsystems for SoCs. Develop micro-architecture specifications and RTL, perform design checks, fix bugs, and collaborate with verification, performance, backend implementation, and project management teams. Support floor planning, constraints, timing closure, and design methodology improvements while guiding team members.

Senior SoC Verification Engineer role at Arm. The provided posting contains salary and company policy information but no detailed responsibilities or qualification requirements.

Architects, implements, and validates design-for-test techniques for Arm SoCs and subsystems. Responsibilities include DFT insertion, RTL and gate-level simulation, ATPG pattern generation, coverage debugging, DFT timing analysis, scan insertion, timing closure, ATE test validation, silicon debug, and characterization. The role collaborates with RTL, verification, physical implementation, test, and product engineering teams throughout development and tape-out.

The Senior/Staff Design Verification Engineer will be responsible for design verification in coherent interconnects. Specific responsibilities are not detailed, but expertise in this area is expected.

Architect and design high-volume SoC platforms using Arm IP across mobile, automotive, datacenter, networking and IoT. Lead cross-functional teams to define platform architecture, optimize performance and power, coordinate IP delivery, drive partner engagements, and influence roadmap and feature development. Guide specification maturity and ensure on-time delivery while driving innovation and continuous improvement.

The SoC RAS Architect drives reliability and serviceability strategies for SoCs, ensuring compliance with data center standards through collaboration with design and engineering teams.

Lead full-chip and block-level timing closure for complex SoCs across project lifecycle. Define and manage timing constraints, collaborate with cross-functional teams and EDA vendors, perform ECOs, address timing for multiple power domains and advanced nodes (5nm/3nm), and automate flows using scripting.