Top Engineering Jobs in Austin, TX

Leads SoC power analysis, modeling, optimization, and pre- and post-silicon power convergence. Manages and mentors power engineers while collaborating with architecture, design, verification, and product teams. Defines power methodologies, workflows, budgets, and sign-off processes; develops workload scenarios; improves accuracy and silicon correlation; and drives performance-per-watt targets throughout the SoC lifecycle.

Staff Design Engineer role at Arm with a stated annual salary range of $198,100 to $268,000. The provided description contains company values, hybrid-work information, application guidance, accommodations, and equal-opportunity statements, but does not specify technical responsibilities, required qualifications, technologies, travel, or clearance requirements.

Build and operate scalable platform services and APIs that improve engineering workflows. Develop Kubernetes operators, automate self-service capabilities, provision cloud infrastructure with Terraform, and manage reliable workloads using AWS, Docker, Kubernetes, Helm, and ArgoCD. Lead technical initiatives, apply secure software engineering practices, support production systems, and participate in an on-call rotation while collaborating across engineering teams.

Define performance telemetry and profiling architecture for next-generation Arm platforms spanning CPUs, accelerators, memory, interconnects, I/O, networking, storage, and chiplets. Establish observability specifications, telemetry models, profiling hooks, and cross-layer data flows from silicon through software and developer tools. Collaborate with hardware, software, power, modeling, and tooling teams to support workload analysis, bottleneck detection, performance validation, power-performance optimization, silicon bring-up, and deployment debugging across AI, edge, automotive, robotics, and infrastructure systems.

Lead performance architecture for next-generation server platforms by analyzing production silicon, AI and HPC workloads, microbenchmarks, cache and memory systems, and high-performance I/O. Define metrics and benchmarking strategies, identify bottlenecks, recommend optimizations, and translate workload and silicon insights into architectural improvements. Collaborate with hardware and software teams while providing technical leadership across complex system-design efforts.

Design and verification engineer for Arm’s next-generation network-on-chip interconnect products. Responsibilities include specifying, creating, and debugging SystemVerilog/UVM constrained-random testbenches; verifying multiprocessing microarchitectures, cache coherence, and AMBA protocols; applying software engineering, scripting, and formal verification skills to ensure reliable, high-performance silicon IP.

Owns component engineering strategy and lifecycle risk management for board-level electronics from architecture and NPI through production and end of life. Responsibilities include component selection, characterization, qualification, alternate-source development, BOM risk analysis, dual-sourcing, obsolescence mitigation, supplier collaboration, reliability support, and component governance. The role partners with Electrical Engineering, Supply Chain, Manufacturing, Quality, suppliers, and contract manufacturers to balance technical performance, reliability, cost, availability, and lifecycle risk.

Develop and deploy Raven, a C++ dynamic random test generator for Arm CPU verification. Responsibilities include implementing verification functionality, creating test templates for architectural and microarchitectural features, debugging user and QA issues, collaborating with CPU verification engineers, and applying computer architecture specifications. The role requires strong C++ development, assembly programming, computer architecture knowledge, and familiarity with CPU verification environments.

Develop cycle-accurate performance models for coherent and non-coherent Arm interconnects. Collaborate with micro-architects, RTL, validation teams, and customers to assess architectural trade-offs, develop features, build performance test suites, identify bottlenecks, and deliver data-driven system performance insights. The role requires strong C++, SystemC TLM, and Python skills, plus expertise in SoC performance modeling and computer architecture.

Develop and analyze memory controller IP and system performance models for Arm-based SoCs. Optimize power, performance, and microarchitecture using workload analysis, simulation, and emulation. Create performance methodologies, identify system bottlenecks, guide internal teams and partners, correlate models with RTL, and mentor engineers. Requires strong computer architecture expertise, C++ development, scripting, and experience with memory or interconnect performance modeling.