Top Engineering Jobs in Austin, TX

Lead quality, functional safety, and automotive cybersecurity compliance for semiconductor and SoC programs. Develop scalable ISO 26262 and ISO/SAE 21434 approaches, align engineering practices with standards, prepare certification evidence, support external assessments, conduct audits, and drive process improvements, training, corrective actions, and safety readiness across automotive, robotics, AI, and industrial products.

Design and validate custom memory circuits for Arm CPUs, GPUs, and SoCs using advanced semiconductor processes. Responsibilities include memory architecture, transistor-level circuit design, layout collaboration, performance-power-area optimization, design margining, physical verification, characterization, front-end verification, release procedures, and quality assurance. The role also involves improving design methodologies and using AI-assisted scripting to increase efficiency and quality.

Lead GPU architecture research and prototyping, collaborate with engineers to develop and validate architectural improvements, perform workload performance analysis (gaming and GPGPU), engage with product teams, and deliver world-class GPU IP through hands-on prototyping and experimental investigations.

Lead cross-functional product engineering for SoC/CPU/GPU manufacturability from pre-silicon readiness through post-silicon bring-up. Own manufacturing flow, ATE/SLT test and correlation, yield improvement, silicon/package reliability qualification, PVTF characterization, and failure analysis while coordinating with foundries, OSATs, design, validation, test, and quality. Support NPI/HVM readiness and audits, with international travel up to 20%.

Lead system-level definition and partner engagements to drive Arm AGI CPU adoption in cloud and data-center markets. Define rack-scale hardware solutions, collaborate with SoC, platform, software, and verification teams, support product requirements, perform competitive analysis, and represent Arm at industry forums to enable scalable, power-efficient server and accelerator deployments.

Lead microarchitecture, RTL development, and integration of high-speed interconnect subsystems (PCIe, CXL, UALink). Translate requirements into synthesizable RTL, collaborate across architecture, verification, firmware, and physical design, analyze traffic and buffering tradeoffs, drive delivery from concept through synthesis and timing closure, mentor engineers, and debug cross-functional issues to meet performance, power, area, and reliability targets.

Lead the development of next-generation system architectures, drive technology objectives, and collaborate with teams to ensure alignment in product goals.

Design and define high-speed on-chip interconnect architectures (coherent and non-coherent) including PCIe, CXL, and UA Link for scalable SoCs. Lead roadmap and early customer architecture engagements, collaborate with performance, power, physical design, software and firmware teams, and perform workload analysis and performance modeling to meet compute, memory, and interconnect targets.

Define and evaluate next-generation CPU microarchitectures for Cortex-X and Neoverse, develop performance models and simulations, analyze workloads, estimate performance/power/area trade-offs, collaborate with design teams and partners, and mentor junior engineers.

Customer-facing technical lead for platform firmware bring-up and debug across silicon, firmware, and OS layers. Support reference and custom platforms, debug DDR/PCIe and multi-socket issues, drive triage and root-cause analysis with internal teams, deliver workshops and documentation, and enable partners to accelerate platform readiness.