Top Engineering Jobs in Austin, TX

The RTL Design Engineer will design and analyze high-performance interconnects, ensuring they meet functional, performance, power, and area goals.

Drive SoC and server platform performance by characterizing real-world AI/HPC workloads on production silicon, designing microbenchmarks, diagnosing bottlenecks, and translating findings into architectural and system-level optimizations while collaborating with hardware and software teams.

Architect and design high-volume SoC platforms using Arm IP across mobile, automotive, datacenter, networking and IoT. Lead cross-functional teams to define platform architecture, optimize performance and power, coordinate IP delivery, drive partner engagements, and influence roadmap and feature development. Guide specification maturity and ensure on-time delivery while driving innovation and continuous improvement.

The SoC RAS Architect drives reliability and serviceability strategies for SoCs, ensuring compliance with data center standards through collaboration with design and engineering teams.

Lead full-chip and block-level timing closure for complex SoCs across project lifecycle. Define and manage timing constraints, collaborate with cross-functional teams and EDA vendors, perform ECOs, address timing for multiple power domains and advanced nodes (5nm/3nm), and automate flows using scripting.

Provide technical mentorship and support to partners integrating Arm CPUs and System IP into SoCs. Perform RTL simulation-based debugging, SoC build reviews, deliver training, influence IP development, test IP, and create knowledge-base content and tooling to improve partner outcomes.

Lead GPU architecture research and prototyping, collaborate with engineers to develop and validate architectural improvements, perform workload performance analysis (gaming and GPGPU), engage with product teams, and deliver world-class GPU IP through hands-on prototyping and experimental investigations.

Lead system-level product engineering for SoC/CPU/GPU silicon from pre-silicon readiness through post-silicon bring-up. Own manufacturability and SLT manufacturing flow, drive yield improvement, characterization, system-level qualification, failure debug, VF margin validation, and cross-functional coordination with design, packaging, validation, test, software, and partners.

Lead cross-functional product engineering for SoC/CPU/GPU manufacturability from pre-silicon readiness through post-silicon bring-up. Own manufacturing flow, ATE/SLT test and correlation, yield improvement, silicon/package reliability qualification, PVTF characterization, and failure analysis while coordinating with foundries, OSATs, design, validation, test, and quality. Support NPI/HVM readiness and audits, with international travel up to 20%.

Lead subsystem-level verification of PCIe and CXL IOs: define verification strategy, craft test plans, develop SystemVerilog/Verilog/UVM testbenches, run simulation/emulation, debug issues, improve methodologies, and mentor junior engineers while coordinating with architects and project managers.