Top Engineering Jobs in Austin, TX

Senior SoC Verification Engineer role at Arm. The provided posting contains salary and company policy information but no detailed responsibilities or qualification requirements.

Architects, implements, and validates design-for-test techniques for Arm SoCs and subsystems. Responsibilities include DFT insertion, RTL and gate-level simulation, ATPG pattern generation, coverage debugging, DFT timing analysis, scan insertion, timing closure, ATE test validation, silicon debug, and characterization. The role collaborates with RTL, verification, physical implementation, test, and product engineering teams throughout development and tape-out.

Lead full-chip and block-level timing closure for complex SoCs across project lifecycle. Define and manage timing constraints, collaborate with cross-functional teams and EDA vendors, perform ECOs, address timing for multiple power domains and advanced nodes (5nm/3nm), and automate flows using scripting.

Design and validate custom memory circuits for Arm CPUs, GPUs, and SoCs using advanced semiconductor processes. Responsibilities include memory architecture, transistor-level circuit design, layout collaboration, performance-power-area optimization, design margining, physical verification, characterization, front-end verification, release procedures, and quality assurance. The role also involves improving design methodologies and using AI-assisted scripting to increase efficiency and quality.

Lead GPU architecture research and prototyping, collaborate with engineers to develop and validate architectural improvements, perform workload performance analysis (gaming and GPGPU), engage with product teams, and deliver world-class GPU IP through hands-on prototyping and experimental investigations.

Lead microarchitecture, RTL development, and integration of high-speed interconnect subsystems (PCIe, CXL, UALink). Translate requirements into synthesizable RTL, collaborate across architecture, verification, firmware, and physical design, analyze traffic and buffering tradeoffs, drive delivery from concept through synthesis and timing closure, mentor engineers, and debug cross-functional issues to meet performance, power, area, and reliability targets.

Lead the development of next-generation system architectures, drive technology objectives, and collaborate with teams to ensure alignment in product goals.

Lead end-to-end ATE secure provisioning for semiconductor manufacturing: define and implement fuse programming and lifecycle transitions, develop/validate Advantest 93K test methods, ensure secure boot and device identity, coordinate with Design/DV/Firmware/Security/Manufacturing, and define production controls, traceability, and guardrails across wafer sort, final test, SLT, and HVM.

As a SoC Emulation Engineer, you'll develop verification testbenches, modify RTL for SoC, and collaborate to define future architectures.

Lead architecture, design, and delivery of coherent and non-coherent SoC interconnect fabrics. Define topology, QoS, latency, bandwidth, and power strategies; drive performance modeling, RTL microarchitecture and verification, debug system-level issues, mentor engineers, and plan interconnect roadmaps while collaborating with CPU/GPU/NPU/memory teams.