Arrow Electronics, Inc.

HQ
Centennial
Total Offices: 15
22,000 Total Employees
Year Founded: 1935
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Arrow Electronics, Inc. Benefits Overview

Compensation + BenefitsCompany CultureWork-Life Balance + WellbeingCareer Growth + Development

Compensation + Benefits

Offers 401(K)

Offers life insurance

Offers occupational accident insurance

Offers disability insurance

Offers supplemental life insurance

Offers accidental death & dismemberment insurance

Offers dental insurance

Offers health insurance

Offers mental health benefits

Offers Flexible Spending Account (FSA)

Offers vision insurance

Offers Health Savings Account (HSA)

Provides family medical leave

Offers generous parental leave

Offers employee discounts

Company Culture

Provides commuter benefits

Offers legal assistance

Utilizes a flexible work schedule

Offers a remote work program

Work-Life Balance + Wellbeing

Offers company-sponsored outings

Offers gym membership

Offers an Employee Assistance Program (EAP)

Offers generous PTO

Provides paid sick days

Provides military leave

Provides paid holidays

Provides bereavement leave

Career Growth + Development

Provides customized development tracks

Job training & conferences

Recently posted jobs

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Arrow Electronics, Inc.

Physcial Design Engineer

One Month AgoSaved
In-Office
2 Locations
Cloud • Enterprise Web • Hardware • Information Technology • Internet of Things • Robotics • Semiconductor
Execute synthesis, place and route, static timing analysis, and physical verification for ASIC partitions. Collaborate with architecture, RTL, DFT, and methodology teams to resolve implementation and signoff issues, close EM/IR, drive LEC, and improve physical design flows. Troubleshoot EDA workflows, work with vendors, implement low-power techniques, and develop custom TCL scripts for Cadence and Synopsys tools. The role is fully onsite in San Jose, California.
Cloud • Enterprise Web • Hardware • Information Technology • Internet of Things • Robotics • Semiconductor
Perform synthesis, place-and-route (PnR), static timing analysis (STA) and signoff for ASIC partitions. Collaborate with architects, RTL and DFT teams to close timing, EM/IR and LEC issues, refine physical design methodologies, troubleshoot flows, and coordinate with EDA vendors to meet tight schedules and design goals.
Cloud • Enterprise Web • Hardware • Information Technology • Internet of Things • Robotics • Semiconductor
Integrates first-party and third-party IP into subsystems and SoCs using Verilog and SystemVerilog. Performs synthesis, timing constraint development, floor-planning analysis, performance optimization, register integration, and design-quality closure through CDC, lint, and RDC checks. Communicates project progress to customers, supports process improvements, resolves complex problems independently, and provides informal guidance to junior staff.
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