Teams at Arrow Electronics, Inc.

Design and verify ASIC RTL using Verilog/SystemVerilog, EDA flows and industry interfaces (PCIe, AXI/APB). Develop scripts, apply low-power UPF, CDC and STA techniques, and use Fusion Compiler/Design Compiler toolchains. Collaborate with customers and report progress while ensuring design signoff and timing closure.

Senior design verification engineer responsible for system-level verification using SystemVerilog/UVM and C/C++ testbenches. Duties include testplan development, building BFM/driver/monitor/scoreboard components, stress and corner testing, failure debug, assertions, coverage closure, gate-level simulations, and customer reporting.

Design and verify FPGA/RTL using Verilog/SystemVerilog, develop scripts, and use EDA tools for simulation, linting, CDC, low-power (UPF) and timing signoff. Work with PCIe and AMBA interfaces, ARM fabric IP, IP-XACT, and report progress to customers. Onsite work at client locations (San Jose or Austin).