Teams at Arrow Electronics, Inc.

Execute synthesis, place and route, static timing analysis, and physical verification for ASIC partitions. Collaborate with architecture, RTL, DFT, and methodology teams to resolve implementation and signoff issues, close EM/IR, drive LEC, and improve physical design flows. Troubleshoot EDA workflows, work with vendors, implement low-power techniques, and develop custom TCL scripts for Cadence and Synopsys tools. The role is fully onsite in San Jose, California.

Perform synthesis, place-and-route (PnR), static timing analysis (STA) and signoff for ASIC partitions. Collaborate with architects, RTL and DFT teams to close timing, EM/IR and LEC issues, refine physical design methodologies, troubleshoot flows, and coordinate with EDA vendors to meet tight schedules and design goals.

Integrates first-party and third-party IP into subsystems and SoCs using Verilog and SystemVerilog. Performs synthesis, timing constraint development, floor-planning analysis, performance optimization, register integration, and design-quality closure through CDC, lint, and RDC checks. Communicates project progress to customers, supports process improvements, resolves complex problems independently, and provides informal guidance to junior staff.