Teams at Cadence Design Systems

Architects and designs processor core logic enhancements in partnership with the Chief Architect. Collaborates with validation and physical design teams to productize solutions, focusing on areas such as load/store, instruction fetch, branch prediction, memory management, and bus protocols. The role may also analyze performance bottlenecks, model improvements, and implement optimization solutions.

Supports Cadence digital implementation and signoff products by debugging customer issues, partnering with R&D and release teams, running design benchmarks, and developing implementation flows. Requires deep expertise in ASIC RTL-to-GDSII methodologies, timing closure, PPA optimization, physical design, low-power and hierarchical design, and industry-standard EDA tools. The role also involves automation using Perl, Tcl, and shell scripting.

Support Cadence Conformal products, especially equivalency checking, by troubleshooting customer issues, debugging systematically, identifying workarounds, and translating findings for R&D. Collaborate with customers and R&D on product features, enhancements, and solutions. Apply RTL synthesis and verification knowledge, scripting skills in Tcl and Perl, technical writing, and strong communication to meet deadlines and resolve ambiguous problems.