Jobs at Cisco

Provide presales cybersecurity expertise for SMB and Mid-Market accounts: partner with sales, translate complex security and networking technologies into solutions, drive technical strategy, engage IT decision-makers, and support customer success and competitive displacement.

Serve as technical lead for customer onboarding, deployments, and high‑severity escalations for Cisco Spaces. Collaborate with Sales and Engineering to run PoVs, resolve complex issues, deploy field trials, build diagnostic tools, refine processes, and enable customers and support teams to maximize product value.

Drive revenue growth across a geo-based territory by engaging new and existing customers, manage full sales cycle, develop enterprise solutions, meet license/support/service revenue targets, and build strong customer relationships while using consultative/solution selling.

Lead the roadmap and architecture for an enterprise-scale AI Development Factory: enable data ingestion, model fine-tuning and deployment, orchestration, governance/guardrails, and observability to ship secure, production-grade AI platforms for global customers.

Lead a team building production AI systems for code generation and developer productivity. Define technical roadmap, drive architecture for distributed training/inference and model serving, partner cross-functionally, establish evaluation/observability/benchmarking practices, and hire and mentor engineering talent to deliver scalable, reliable AI-powered developer tooling.

Lead research, design, and deployment of large-scale foundation models for machine-generated data (logs, time series, traces). Define AI strategy, mentor senior engineers, partner with product and exec teams, and drive production-grade model training, optimization, and MLOps for enterprise-scale applications.

Lead SRE to architect and operate resilient hybrid-cloud (GCP + on-prem) Kubernetes platforms, enforce IAM and quota policies, secure and scale microservices, implement automation (Terraform/Docker), design observability via Elasticsearch/Kibana, and integrate security-by-design with Apigee and development teams.

Lead strategic sourcing and partner management for EMS/OEM/ODM partners to optimize Ciscos supply chain. Develop and execute end-to-end sourcing strategies, drive negotiations and cost reduction using data-driven insights, collaborate with cross-functional teams, and implement continuous improvement initiatives across product lifecycles.

Lead verification of next-generation 100G–1.6T coherent optical ASICs: create test plans and benches, apply advanced verification techniques, supervise execution, drive chip-level tradeoffs, review coverage and code, mentor engineers, and improve verification processes.

Lead full-chip ASIC physical design including floorplanning, RTL-to-GDSII implementation, clock mesh/HTree design, power grid planning, STA, power integrity, physical verification, and tool/flow improvements while collaborating with RTL, package, foundry, IP vendors, and EDA teams.

Serve as primary account owner for high-tier customers, managing complex, multi-stakeholder sales cycles. Build C-suite relationships, drive cross-portfolio growth, lead negotiations, forecast and plan accounts, and coordinate cross-functional teams to align networking solutions with customer goals.

Lead RTL-to-GDSII implementation for advanced nodes (sub-16nm to 3nm). Define floorplanning, place-and-route, clock and power distribution, and timing convergence. Perform STA, timing sign-offs, and timing ECOs; develop STA automation scripts. Collaborate with RTL/DFT teams and EDA vendors to improve flows, debug timing, and drive methodology alignment.

Lead full-chip physical design including floorplanning, partitioning, pin assignment, clock and power-grid planning, place-and-route, STA, power integrity, verification and signoff. Collaborate with system, package, RTL, DFT, EDA vendors and foundry/IP partners. Improve tool flows and methodologies, apply low-power UPF techniques, and leverage AI tools for productivity enhancements.

Design and implement AI-driven business processes: map workflows using BPMN, integrate LLMs and AI agents, deploy ML models with MLOps/CI-CD on cloud, monitor KPIs, ensure compliance, and collaborate cross-functionally to optimize supply chain operations.

Lead full-chip physical design: floorplanning, partitioning, pin/bump assignment, clock planning, power-grid planning, place-and-route, STA, power integrity, physical verification and equivalence checks. Improve EDA flows, collaborate with RTL/DFT/package/foundry/IP teams, use UPF for low-power design, and apply Python and AI tools to boost productivity.

Lead RTL-to-GDSII implementation for advanced nodes (sub-16nm to 3nm), owning floorplanning, place-and-route, clock/power distribution, timing convergence, STA sign-offs, ECOs, tool/flow optimization, and cross-team collaboration with RTL, DFT, and EDA vendors.

Lead semiconductor manufacturing operations transformations by aligning business strategy with technology. Design optimized supply chain workflows, configure Oracle ERP for discrete manufacturing, enable B2B transactions, support MES and partner onboarding, use analytics and AI to drive insights, and collaborate with IT and leadership to measure and improve operational performance.

Lead end-to-end semiconductor supply chain transformation by translating strategy into roadmaps, designing optimized processes, enabling Oracle ERP transformations, using analytics and AI, mentoring architects, and establishing governance to drive measurable business outcomes.

Lead global Manufacturing vertical AI go-to-market: define strategy, drive pipeline and bookings, align cross-functional teams, build partner and customer lighthouse accounts, coach sellers, and lead executive engagements to scale AI solutions.

Lead global AI go-to-market for Financial Services: define vertical strategy, own pipeline/P&L, drive executive engagements, coach matrixed sellers, build partner and lighthouse customer programs, and scale solution-led motions to meet revenue targets.