Jobs at Cornelis Networks

Lead SoC verification strategy and execution: design UVM/SystemVerilog testbenches, run regressions, drive coverage closure, debug RTL failures, collaborate with design/emulation/silicon teams, and mentor verification engineers to ensure first-pass silicon success.

Develop and maintain SAI and switch SDK components for next-generation ASIC platforms, integrate with NOS like SONiC, build test/CI frameworks, optimize performance, collaborate with hardware and firmware teams, and mentor engineers.

Lead product management for storage ecosystem qualification of Cornelis NICs and switches. Drive technical validation, partner certification, roadmap alignment, GTM activation, and cross-functional coordination with storage providers, sales, and engineering to secure design wins and ensure high-performance end-to-end AI/HPC solutions.

Lead NOS platform porting and BSP development for switch ASICs, integrate and validate drivers, hardware monitoring and BMC interfaces, implement control/data plane components for SONiC and FBOSS, build test infrastructure and CI/CD, profile and optimize performance, and collaborate across hardware, firmware, and SAI/SDK teams while engaging with open-source communities.

Design and optimize AI communication middleware for distributed multi-node, multi-GPU training. Implement C/C++ performance-critical features, improve GPU communication paths, profile and tune frameworks (PyTorch, TensorFlow, JAX, DeepSpeed), develop benchmarks, contribute upstream, and collaborate with kernel, driver, switch, and systems teams to validate and deploy high-performance networking for AI/HPC.

Lead SOC-level verification strategy and execution for high-performance AI/HPC networking ASICs. Drive UVM/SystemVerilog testbench development, regressions, coverage closure, RTL debug, cross-functional collaboration, and mentor verification teams to ensure first-pass silicon success.

Lead design and implementation of Kubernetes integration for Cornelis Networks' fabric management: build Go-based operators/controllers, extend Kubernetes for specialized hardware and scheduling, enable cloud-native orchestration of fabric services, collaborate across platform and hardware teams, contribute upstream, and document best practices while leveraging AI-assisted development tools.

Lead integration and validation of PCIe controllers in SoCs, optimize PCIe stack performance, drive silicon bring-up and lab validation, debug RTL/gate/silicon issues, ensure PCIe compliance, collaborate across IP, verification, physical design and software teams, and mentor junior engineers.