Jobs at Cornelis Networks

Lead verification closure for complex ASICs, SoCs, and networking hardware. Define verification strategies, develop UVM testbenches, create functional tests, debug RTL failures, and close functional and code coverage. Collaborate with design, software, emulation, hardware, and silicon validation teams. Guide and mentor verification engineers while establishing coding and verification standards and applying AI tools to improve team productivity.

Drive planning and execution of software initiatives for HPC and AI networking products. Manage schedules, milestones, dependencies, releases, risks, dashboards, and decision records while coordinating software, firmware, hardware, platform, validation, product, and field teams. Support release readiness, customer-impacting issue resolution, prioritization, and engineering-process improvements. Communicate progress and tradeoffs to technical teams, executives, and customer-facing stakeholders.

Design and implement RTL for high-speed ASIC data paths and packet-processing logic using Verilog and SystemVerilog. Collaborate on verification, timing constraints, physical design, post-silicon validation, system debugging, and power-aware performance optimization for AI and HPC networking systems.

Develop and maintain AI-based ASIC verification automation flows, regression infrastructure, dashboards, reporting tools, and triage automation. Build scripts and integrations using Python, Perl, Tcl, shell scripting, and Make. Support simulation, coverage, lint, formal, emulation, continuous integration, EDA tool integration, and distributed compute infrastructure. Debug automation, tool, runtime, licensing, queue, and workflow issues while improving verification reliability, reproducibility, and efficiency across geographically distributed engineering teams.

Lead and grow the RTL design engineering team responsible for next-generation networking ASICs. Own RTL delivery schedules, coordinate design verification, emulation, and physical design dependencies, manage timing-closure and tape-out readiness, identify schedule risks, and allocate resources. Develop headcount and organizational plans, lead hiring, and scale globally distributed engineering practices while contributing hands-on expertise in microarchitecture, RTL design, synthesis, verification, and PPA optimization.