Teams at Cornelis Networks

Lead end-to-end PCIe IP integration into complex ASIC and SoC designs, collaborating across architecture, verification, physical design, software, and external IP vendors. Optimize PCIe performance, contribute to IO and interconnect architecture, and lead silicon bring-up, interoperability testing, and debugging across RTL, gate-level, emulation, and post-silicon environments. Mentor engineers and establish PCIe subsystem development practices for high-performance AI and HPC platforms.

Lead verification closure for complex ASICs and SoCs used in AI and high-performance computing networking. Define verification strategies, develop UVM/SystemVerilog testbenches, execute functional testing, debug RTL failures, and close functional and code coverage. Guide block, subsystem, and SoC verification while collaborating with design, software, emulation, hardware, and post-silicon teams. Mentor engineers, establish verification guidelines, and promote AI tools to improve team productivity.

Lead end-to-end execution of complex networking product programs, coordinating cross-functional teams (ASIC, platform, software, validation, manufacturing) to deliver scalable AI/HPC interconnect solutions on time and within budget. Manage timelines, budgets, risks, reporting, stakeholder reviews, and mentor program managers and engineering leads while promoting agile and lifecycle best practices.