Jobs at Intel

The role involves developing layout design methodologies, integrating full-chip SoC designs, collaborating with various teams, and ensuring scalable solutions for testchip platforms.

Lead and execute ASIC/SoC verification: define verification strategies, develop SystemVerilog/UVM environments, run simulations and formal checks, debug pre-silicon issues, analyze power/performance, collaborate with architects and RTL teams, improve verification methodologies, and mentor junior engineers.

Lead emulation and FPGA modeling from RTL through synthesis and partitioning to enable presilicon verification and software development. Develop, integrate, test, and debug hardware/software in simulation, emulation, and FPGA models; create tools and automation to improve emulation efficiency; optimize performance and debug failing RTL tests; collaborate with cross-functional teams and mentor engineering leaders.

The CPU Physical Design Engineer will implement custom CPU designs, conduct physical design flow, optimize designs, and collaborate on verification processes. They will work with EDA vendors and enhance methodologies for CPU design.

Develop communication libraries for high-performance computing, optimizing software, collaborating with scientists, and resolving distributed computing challenges.

As a CPU Physical Design Engineer, you'll implement custom CPU designs from RTL to GDS and conduct all aspects of the physical design flow including synthesis, place, and route. You'll verify designs and collaborate with various teams to enhance microarchitectures.

The role involves performing physical design implementation, conducting verification and signoff, optimizing CPU design, and collaborating with various teams. Key responsibilities include synthesis, place and route, and static timing analysis.

Design and optimize advanced embedded memory IP (SRAM, register files, ROM) for Intel CMOS processes. Perform memory pathfinding, PPA optimization, custom circuit design, layout and automation, pre-silicon verification and post-silicon validation/debug to enable yield and product ramp. Collaborate with domain experts, EDA vendors, and product teams to deliver memory collaterals and test chips.

The CPU Memory Design Engineer will design and develop custom memories and digital circuits for Intel CPUs, focusing on low-power and high-performance memory designs.

Design and develop custom and compiler-based memory circuits including SRAMs and caches, focusing on high-performance and low-power implementations.

Design and integrate SoC logic: develop RTL (SystemVerilog), collaborate on microarchitecture, integrate/validate IPs, optimize for power/performance/timing, support verification and pre-silicon validation, and ensure secure development and production readiness.

Design and optimize analog and mixed-signal circuits (power delivery, IPs) for advanced CMOS nodes. Perform circuit simulation, floor-planning, post-layout extraction, verification, and validation. Collaborate with architecture, layout, and validation teams, analyze test data, and iterate designs to meet power, performance, area, timing, yield, and robustness goals.

Design and implement CPU microarchitecture and RTL with emphasis on power management and energy efficiency. Develop SystemVerilog/Verilog RTL, drive PPA optimization, design CDC solutions, support DVFS, power/thermal management, reset and power-state transitions, debug complex RTL, and collaborate with verification, physical design, and SoC integration teams to deliver full-chip solutions.

The role involves architecting and leading the development of a neuromorphic AI execution stack, focusing on firmware, runtime, and performance infrastructure while collaborating with multiple teams for integration and optimization.

Design, implement, and optimize Intel's neuromorphic AI compiler and runtime. Build tooling for performance analysis, verification, debugging, and optimization. Integrate the software stack with robotics and edge AI ecosystems. Collaborate with hardware, compiler, and systems teams and external customers to deliver production-grade, high-performance software.

Seek a Senior CPU Power Management Architect for creating and ensuring optimal performance in CPU designs, focusing on power management architecture, collaboration across teams, and post-silicon debugging.

Design and optimize CPU logic and RTL, write and simulate RTL for CPU IP blocks, meet PPA and timing goals, ensure physical design integrity, review verification plans, document microarchitectural specs, and collaborate with SoC customers for integration.

Design and implement mixed-signal IP logic: RTL coding, simulation, and optimization to meet power, performance, area, and timing goals. Collaborate with analog, digital, and physical teams, review and fix RTL verification issues, and support SoC customers for high-quality IP integration.

Lead the development and governance of analog/mixed-signal design environments. Oversee EDA tool ecosystems, compute infrastructure, design data governance, and tapeout management. Manage engineers, collaborate with IT, and optimize design flows to enhance productivity and reproducibility.

Lead physical design timing efforts for next-generation SoCs: perform timing analysis and optimization, generate and validate timing constraints, define PVT conditions, develop timing models and flows, collaborate with clocking, architecture, and logic teams to ensure high-performance, low-power chip integration.