Jobs at Intel

Develop and optimize compiler tools targeting Intel CPUs, GPUs, and accelerators. Responsibilities include adding compiler features, integrating processor capabilities, maintaining LLVM, Clang, SYCL, and Fortran frameworks, debugging, performance analysis, vectorization, parallelization, benchmarking, and open-source collaboration. The role supports AI and high-performance computing applications and involves cross-functional work with hardware, validation, and global engineering teams.

Design and verify high-performance CPU physical designs from RTL synthesis through GDSII. Responsibilities include floorplanning, placement and routing, clock implementation, timing and power analysis, formal equivalence, DRC/LVS, reliability verification, automation workflow development, and collaboration with architecture, logic, circuit, automation, and EDA vendor teams.

Develop semiconductor product yield methods, models, and analytics for advanced logic process nodes. Analyze fab, defect, electrical, and process data using statistics, machine learning, and coding to identify yield limiters and root causes. Drive process improvements, manufacturability, product introductions, design-technology co-optimization, and design of experiments. Build measurement recipes, computational tools, and AI/ML applications while collaborating with design teams, equipment vendors, and manufacturing organizations.

Develops semiconductor product yield analysis solutions for advanced-node technology. Responsibilities include mathematically modeling yield problems, identifying root causes of systematic yield issues, creating analysis methods and algorithms, debugging process/product interactions with design teams, and presenting yield improvement strategies to leadership. Collaborates with program managers, process integration, device integration, and defect teams to improve production yield.

Leads development and validation of density-fill methodologies and PDK physical verification solutions for advanced semiconductor nodes. Develops algorithmic solutions using Calibre, Synopsys ICV, and Cadence Pegasus; debugs rule decks; builds validation frameworks; automates engineering workflows; collaborates with process, design, CAD, and EDA teams; and contributes technical expertise to design enablement roadmaps.

Supports sales operations by coordinating customers, sales teams, business units, and factories to optimize supply, revenue, and order fulfillment. Manages order processes, invoicing, expedites, changes, RMAs, and supply chain compliance. Uses SAP and data analysis to improve business processes, data quality, forecasting, and operational performance across semiconductor manufacturing operations.

Lead semiconductor product yield development for advanced-node manufacturing. Formulate and resolve yield problems, develop validation plans, analyze test results, troubleshoot design and manufacturing issues, and optimize product and process methodologies. Collaborate with cross-functional stakeholders, guide roadmap execution, remove technical barriers, and introduce emerging technologies to improve product quality, reliability, performance, and manufacturing efficiency.

Develop and maintain frontend and backend applications for semiconductor manufacturing and factory automation systems. Design scalable automation solutions, implement testing across multiple levels, automate CI/CD processes, troubleshoot deployed systems, and collaborate cross-functionally on requirements and architecture. The role also applies Agentic AI and GenAI platforms to improve manufacturing automation and decision-making.

Develops and executes verification plans and testbenches for interconnect and chassis IPs at IP and subsystem levels. Builds reusable verification components, checkers, constrained-random tests, and debug infrastructure; analyzes simulation failures; drives bug resolution; and supports functional coverage closure, simulation, formal verification, and regression automation. Collaborates with architecture, design, and software teams to deliver reliable first-pass silicon.

Performs low-level SoC and subsystem debugging, root-cause analysis, failure triage, bench testing, and product characterization. Develops debug tools, scripts, requirements, and design-for-debug techniques while collaborating with design, validation, and manufacturing teams to improve reliability, readiness, and debug workflows.

The role involves analyzing user information, documenting business processes, training users, supporting testing, and managing data configurations with Windchill PLM.

Perform functional verification of mixed-signal logic components by developing verification plans, testbenches, and environments; run system simulations; debug presilicon issues; collaborate with architects, RTL and physical design teams; document and improve verification infrastructure and methodology.

Leads demand planning, Sales and Operations Planning, and long-range planning for semiconductor foundry operations. Manages production and engineering demand, product roadmaps, forecasts, capacity allocation, inventory, and supply readiness. Collaborates with business development, engineering, operations, and supply chain teams to identify risks, improve forecast accuracy, and align material, vendor, customer, and manufacturing capacity with projected demand.

Leads sales operations and revenue programs for Intel Foundry, coordinating cross-functional stakeholders, supply chain activities, customer engagement, and business readiness. Owns program lifecycle management, reporting, risk resolution, process improvements, and revenue optimization activities. Requires semiconductor or manufacturing experience, sales or finance analytics expertise, supply chain planning systems knowledge, and advanced Excel skills.

Designs and develops advanced full-custom and compiler-based memory circuits, including SRAMs, caches, register files, ROMs, and custom memories. Responsibilities include circuit simulation, characterization, cache and critical-path analysis, memory architecture, bit-cell and peripheral design, automation, PPA optimization, methodology development, and cross-functional execution for advanced CMOS CPU and SoC products.

Leads large-scale technical programs spanning design-technology co-optimization, circuit design, foundational IP, and design enablement. Partners with engineering teams, customers, EDA vendors, and ecosystem stakeholders to align technical strategy, drive execution, improve organizational processes, and represent program roadmaps to senior leadership. Responsibilities also include mentoring engineers, workforce development, hiring, training, budget planning, and organizational transformation.

Leads business development for Intel’s neuromorphic computing portfolio, identifying strategic opportunities across robotics, edge AI, autonomous systems, sensing, communications, and aerospace. Builds customer and partner relationships, drives evaluations and proof-of-concepts toward commercial deployment, develops ecosystem partnerships, translates market needs into product priorities, assesses competitors and trends, shapes go-to-market strategies, represents the lab externally, and manages the opportunity pipeline.

Develops and maintains SystemVerilog and UVM verification environments for PLL and FLL clock-generator IPs. Performs functional and mixed-signal validation, creates test plans, debugs pre-silicon issues, and root-causes failures. Collaborates with architects, RTL developers, and analog design teams to verify microarchitectural requirements, refine methodologies, and support multiple IP generations.

Develop and maintain transistor-level timing characterization flows for custom IP, memories, SRAMs, register files, and compiler-generated macros. Build CAD infrastructure, automation, and validation methodologies for timing, power, and noise models. Collaborate with circuit design, memory, STA, methodology, and EDA vendor teams. Support hardware design, verification, integration, layout, and timing development for advanced semiconductor technology nodes.

Performs CPU physical design from RTL through GDS, including synthesis, floor planning, placement and routing, clock tree synthesis, timing closure, power and reliability analysis, and signoff verification. The role optimizes CPU designs for power, frequency, and area; collaborates with architecture, logic, circuit, automation, and EDA vendor teams; develops physical design methodologies; and supports tapeout on advanced process technologies.