Jobs at Intel

Develops logic design, RTL coding, and simulation for a CPU, ensuring design integrity, and supports SoC customers for integration.

The role involves architecting and leading the development of a neuromorphic AI execution stack, focusing on firmware, runtime, and performance infrastructure while collaborating with multiple teams for integration and optimization.

Seek a Senior CPU Power Management Architect for creating and ensuring optimal performance in CPU designs, focusing on power management architecture, collaboration across teams, and post-silicon debugging.

The Senior CPU Physical Design Engineer will work on high-performance CPU design, conducting verification, and collaborating with teams to optimize CPU microarchitectures and enhance tools and methodologies.

Define, design, and develop RF integrated circuits; create verification plans, perform analysis, and ensure designs comply with specifications in a collaborative environment.

As a SAP Master Data Architect, you will manage and innovate SAP product master data structure, support end-to-end implementations, and ensure data quality and governance, collaborating with teams across the organization.

The role involves leading RTL coding and design for high-performance CPUs, collaborating with architecture teams, and ensuring design integrity and efficiency.

The CEG Technical Assistant/Chief of Staff supports CEG's strategic initiatives, managing executive operations, stakeholder relationships, and driving business objectives. Responsibilities include collaboration across Intel, facilitating communication amongst teams, and enhancing organizational processes.

As a Formal Verification Engineer, you'll ensure reliability of Intel's IP and SoC microarchitectures by developing verification plans, collaborating with teams, and utilizing formal verification tools and methodologies.

The CPU Design Verification Engineer will validate Intel's ATOM processors by developing verification plans, executing simulations, and collaborating with various engineering teams to ensure performance and correctness.

Lead the development and governance of analog/mixed-signal design environments. Oversee EDA tool ecosystems, compute infrastructure, design data governance, and tapeout management. Manage engineers, collaborate with IT, and optimize design flows to enhance productivity and reproducibility.

The engineer will design high-performance microprocessors, leading methodologies, collaborating with teams, and enhancing silicon development efficiency with AI tools.

Develop logic design and RTL coding for SoC designs, integrate IP blocks, perform quality checks, and collaborate with verification teams. Lead architectural evaluations, define micro-architecture, optimize logic for power and performance, and mentor junior engineers.

The Consumer Industries Solution Lead at Intel will manage strategic roadmaps and develop AI-driven solutions for retail and transactional systems, requiring strong collaboration and industry expertise.

Develop logic design and RTL coding for AI SoC products, integrate IP blocks, perform quality checks, and mentor junior engineers.

The Senior Executive Compensation Analyst will design and manage compensation programs, conduct market research, ensure compliance, and collaborate with cross-functional teams to support executive pay strategies.

The role involves leading pre-silicon verification of CPU designs, developing verification plans, debugging RTL issues, collaborating with design teams, and documenting results.

As a SOC Performance Architect, you will work with design and architecture teams to improve performance of XEON CPU and AI products, evaluate hardware features, and resolve design weaknesses.

Design and develop custom digital circuits for Intel CPUs, focusing on optimization and collaboration with cross-functional teams to enhance CPU technology.

Lead development and execution of CPU functional verification plans. Build scalable UVM testbenches, run system-level simulations, debug pre-silicon issues, collaborate with architects and RTL designers, document strategies, and maintain verification infrastructure to ensure CPU logic correctness.