Jobs at Intel

Design and optimize CPU RTL logic, simulations, and microarchitectural features for Intel processors. Develop power-, performance-, area-, and timing-efficient designs; resolve RTL test failures; document microarchitectural specifications; support physical implementation; and collaborate with architecture, verification, integration, and SoC customer teams. The role also involves clock-domain crossing, power-aware design, timing convergence, and CPU power-management considerations.

Leads full-chip floorplanning, physical integration, tapeout, and physical verification for advanced-node semiconductor testchips and silicon vehicles. Develops custom layout methodologies and automation using Tcl, Python, or SKILL; resolves DRC, LVS, DFM, density, and antenna issues; collaborates with PDK, EDA, technology development, and manufacturing teams; and coordinates tape-in readiness, database integrity, and project execution for FinFET and GAA technologies.

Conduct research in neuromorphic AI for edge computing, robotics, signal processing, control, and autonomous systems. Design algorithms, develop research software, build benchmarks, and optimize models for sparsity, latency, memory, quantization, and energy efficiency. Collaborate with hardware and software teams to define architectures, create customer prototypes, publish findings, and advance neuromorphic computing toward commercial applications.

Develop pre-silicon verification methodologies for neuromorphic SoC and ASIC architectures across software, RTL, and emulation platforms. Create Python-based directed and random tests, map application requirements to test plans, run regressions, debug failures, track coverage, maintain assertions and scoreboards, and integrate verification IPs. Collaborate with architecture, design, software, and IP teams to validate protocols and improve first-pass silicon success.

Design and optimize complex analog layouts using Cadence and Calibre tools; perform DRC/LVS and reliability checks; floorplan, power-grid, ESD and bump layout work; collaborate with circuit, process, and extraction teams to debug and improve layout quality and performance.

Lead strategy, roadmap, and execution for Intel’s data center AI software portfolio. Define enterprise-ready generative AI, agentic, microservices, and turnkey solutions across cloud, hybrid, and on-premises environments. Analyze competitors, develop go-to-market positioning, and grow relationships with cloud providers, ISVs, neoclouds, and open-source communities. Partner with engineering, AI research, silicon architecture, documentation, and developer relations teams to deliver PRDs, deployment blueprints, APIs, SDKs, and validated software offerings.

Design and develop RTL logic for CPU components and IP blocks. Contribute to CPU architecture and microarchitecture, optimize power, performance, area, and timing, support verification, resolve RTL test failures, document specifications, and assist SoC customers with CPU block integration.

Leads global accounting teams responsible for Intel’s consolidated financial close, financial statement consolidation, management reporting, cash flow reporting, and financial analysis. Oversees SEC reporting support, auditor requests, controls, process improvements, and finance transformation initiatives. Partners with senior leadership and cross-functional stakeholders to ensure accurate, timely reporting and actionable insights. The role requires CPA certification, extensive corporate accounting experience, public accounting background, and leadership of global teams.

Leads a global accounting team responsible for management reporting, balance sheet and cash flow analysis, executive reporting, and consolidated financial results. Partners on SEC filings, audits, close and consolidation processes, and cross-functional financial reporting. Drives process improvement, automation, reporting controls, and AI-enabled transformation while translating financial results into insights for senior leadership.

Verifies CPU logic and microarchitecture through test plans, test benches, simulations, and verification environments. The engineer debugs presilicon failures, analyzes power and timing, improves verification infrastructure, and collaborates with architects, RTL developers, and physical design teams to ensure functional, performance, and power objectives are met.

Leads the design, governance, and scaling of enterprise AI technical and functional learning programs. Builds persona-based learning pathways, partners with AI engineers and instructional designers on training content, oversees instructor-led and self-paced delivery, manages learning vendors, and uses feedback, metrics, and dashboards to improve workforce AI readiness.

Lead end-to-end architecture for modular, scalable SoCs supporting datacenter and agentic computing. Define hardware, firmware, functional specifications, microarchitectures, registers, and performance goals; integrate IP blocks; develop validation infrastructure; analyze benchmarks; and optimize power, timing, performance, and area. Collaborate across architecture, design, systems, and verification teams, influence technology roadmaps, provide technical leadership, and mentor other engineers.

Designs and develops advanced full-custom and compiler-based memory circuits, including SRAMs, caches, register files, ROMs, and custom memories. Responsibilities include circuit simulation, characterization, cache and critical-path analysis, memory architecture, bit-cell and peripheral design, automation, PPA optimization, methodology development, and cross-functional execution for advanced CMOS CPU and SoC products.

Lead front-end silicon design and verification for neuromorphic chiplets, IP, processors, and AI accelerators. Translate architectures into microarchitectures, manage design through post-silicon validation, integrate high-speed interfaces and external IP, collaborate on physical design and custom memories, enable pre-silicon software development, and mentor multidisciplinary engineering teams. The role requires ownership of product tape-outs and experience with advanced ASIC methodologies.

Two-year full-time rotational program developing sales, marketing, technical sales, and business skills through three eight-month rotations. Participants support sales strategies, marketing campaigns, customer engagement, business operations, and communications initiatives while building product, technology, customer, analytical, leadership, and communication expertise.

Two-year, three-rotation program developing technical sales and marketing talent. Participants rotate through sales engineering, technical marketing, solution architecture, and related roles while building expertise in Intel products, technologies, customers, sales channels, and industry ecosystems. Responsibilities include developing technical solutions, influencing customer adoption, delivering quarterly objectives, and strengthening leadership, communication, and customer skills through mentoring and customized training.

Designs and optimizes custom and compiler-based embedded memory solutions for high-performance, low-power CPUs and SoCs. Responsibilities include SRAM, cache, register file, ROM, memory array, bit-cell, and peripheral circuit design; characterization and simulation; critical-path analysis; PPA optimization; automation; methodology development; and cross-functional collaboration with architecture, layout, process, physical design, and validation teams.

Develop and optimize Intel SHMEM, MPI, MPICH, and oneCCL communication libraries for low latency, high bandwidth, and reliability. Collaborate with cross-functional teams to define software requirements, debug across hardware and software layers, and support high-performance scientific computing and machine learning on Intel CPUs and GPUs.

Develop and maintain Intel’s asynchronous EDA design automation flow for neuromorphic silicon. Build algorithms, tools, utilities, scripts, and regression tests supporting RTL, verification, physical design, simulation, FPGA emulation, synthesis, and implementation. Create scalable frameworks for early software development and optimize custom low-power, high-performance designs. The role requires full ASIC lifecycle knowledge, multiple tape-outs, strong scripting skills, and experience using AI-assisted engineering tools.

Design and optimize analog and mixed-signal circuits and foundational IP, including ADCs, DACs, voltage regulators, and high-speed I/O. Responsibilities include circuit simulation, floorplanning, verification, tape-out, test planning, post-silicon debugging, and collaboration with architecture, layout, process technology, IP, and product teams.