Jobs at Intel

Develops and maintains SystemVerilog and UVM verification environments for PLL and FLL clock-generator IPs. Performs functional and mixed-signal validation, creates test plans, debugs pre-silicon issues, and root-causes failures. Collaborates with architects, RTL developers, and analog design teams to verify microarchitectural requirements, refine methodologies, and support multiple IP generations.

Design and optimize analog and mixed-signal circuits and foundational IP, including ADCs, DACs, voltage regulators, and high-speed I/O. Responsibilities include circuit simulation, floorplanning, verification, tape-out, test planning, post-silicon debugging, and collaboration with architecture, layout, process technology, IP, and product teams.

Optimize LLM inference on Intel GPUs by profiling performance bottlenecks, developing custom kernels, and improving attention, MoE, quantization, and operator fusion. Contribute optimizations to vLLM, SGLang, and PyTorch, perform roofline analysis, support scale-out inference, and collaborate with architecture and compiler teams to influence future GPU roadmaps.

Develop and maintain transistor-level timing characterization flows for custom IP, memories, SRAMs, register files, and compiler-generated macros. Build CAD infrastructure, automation, and validation methodologies for timing, power, and noise models. Collaborate with circuit design, memory, STA, methodology, and EDA vendor teams. Support hardware design, verification, integration, layout, and timing development for advanced semiconductor technology nodes.

Performs CPU physical design from RTL through GDS, including synthesis, floor planning, placement and routing, clock tree synthesis, timing closure, power and reliability analysis, and signoff verification. The role optimizes CPU designs for power, frequency, and area; collaborates with architecture, logic, circuit, automation, and EDA vendor teams; develops physical design methodologies; and supports tapeout on advanced process technologies.

Develops and maintains ESD and latch-up rule decks, reliability design methodologies, and PDK verification solutions for advanced Intel process technologies. Builds test cases, validates and debugs rule checks, defines QA requirements, and automates verification workflows. Collaborates with design, reliability, CAD, and external EDA vendor teams to implement tool features, resolve design issues, improve robustness, and lead cross-functional innovation initiatives.

Develop and execute pre-silicon SoC power, thermal, and performance validation and optimization plans. Collaborate with architecture, design, firmware, and software teams; debug failures; collect and analyze thermal data; maintain validation infrastructure; develop testing environments; produce reports; and improve validation methodologies. The three-year contract role supports Intel’s Data Center Group and uses simulation, emulation, performance monitoring, and hardware/software optimization techniques.

Implements and optimizes CPU physical designs from RTL through manufacturing-ready databases. Responsibilities include floorplanning, synthesis, place and route, clock tree synthesis, static timing analysis, power optimization, verification, signoff, layout checks, and design automation. The engineer collaborates with architecture, logic, circuit, validation, automation, and EDA teams to improve performance, power, area, timing, manufacturability, and physical design methodologies.

Design, implement, analyze, and optimize clock distribution networks for high-performance CPU and SoC products. Responsibilities include clock architecture, clock tree synthesis, timing analysis and closure, custom circuit and library-cell development, power-performance-area optimization, automation scripting, and collaboration across architecture, physical design, validation, and EDA teams.

Designs and develops advanced memory circuits, including SRAMs, caches, register files, ROMs, and custom memory IP for CPU and SoC products. Responsibilities include circuit simulation, characterization, PPA optimization, variation analysis, memory path-finding, and collaboration with architecture, process, physical design, and product engineering teams.

Perform functional verification of mixed-signal logic components by developing verification plans, testbenches, and environments; run system simulations; debug presilicon issues; collaborate with architects, RTL and physical design teams; document and improve verification infrastructure and methodology.

Designs cache subsystems for Intel AI SoCs, including microarchitecture, RTL coding, integration, simulation, timing constraints, and verification. Evaluates power, performance, and area tradeoffs; supports synthesis, timing closure, formal equivalence, silicon bring-up, post-silicon validation, and debugging. Requires advanced Verilog/SystemVerilog expertise, SoC integration experience, bus protocol knowledge, scripting skills, and leadership in mentoring engineers and improving design methodologies.

Develops AI-assisted CAD/EDA automation, tools, and workflows for RTL design and verification. Responsibilities include troubleshooting EDA tools, building simulation and regression automation, improving CI/CD, analyzing infrastructure performance, supporting emulation and static sign-off, and collaborating with design, verification, infrastructure, cloud, and EDA vendor teams.

Develops semiconductor product yield methods and models for advanced logic technologies. Analyzes fab, defect, electrical, and process data using statistics, machine learning, and coding to identify yield limiters and root causes. Creates algorithms, measurement recipes, and AI/ML tools to improve manufacturability, product quality, and production ramp. Collaborates with design, manufacturing, equipment vendors, and cross-functional teams on process changes, new product introductions, experiments, and design-technology co-optimization.

Lead pre-silicon functional verification of Atom CPU cores: develop verification plans, SystemVerilog/UVM testbenches, run system-level simulations, debug RTL/microarchitecture issues, collaborate with architects and design teams, and improve verification infrastructure and automation to ensure correctness, performance, and power-efficiency before first silicon.

Develop scalable verification plans, test benches, and environments for complex SoC designs. Execute emulation and system simulation tests, debug presilicon issues, improve functional verification infrastructure, and collaborate with architecture, RTL, physical design, and postsilicon teams. Integrate security coverage, maintain test plans, and incorporate postsilicon feedback into presilicon verification strategies.

Design and scale silicon spin-qubit processors from PDK development through tapeout, fabrication, validation, and system integration. Responsibilities include qubit standard-cell design, automated placement and routing, signal integrity and thermal analysis, customized EDA capabilities, PDK collateral, design-rule validation, interposer interfaces, and electrical characterization structures. The engineer collaborates with quantum, control, packaging, process, lithography, software, and external customer teams to enable large-scale quantum processor designs.

Conduct research in neuromorphic AI for edge computing, robotics, signal processing, control, and autonomous systems. Design algorithms, develop research software, build benchmarks, and optimize models for sparsity, latency, memory, quantization, and energy efficiency. Collaborate with hardware and software teams to define architectures, create customer prototypes, publish findings, and advance neuromorphic computing toward commercial applications.

Develop pre-silicon verification methodologies for neuromorphic SoC and ASIC architectures across software, RTL, and emulation platforms. Create Python-based directed and random tests, map application requirements to test plans, run regressions, debug failures, track coverage, maintain assertions and scoreboards, and integrate verification IPs. Collaborate with architecture, design, software, and IP teams to validate protocols and improve first-pass silicon success.

Lead strategy, roadmap, and execution for Intel’s data center AI software portfolio. Define enterprise-ready generative AI, agentic, microservices, and turnkey solutions across cloud, hybrid, and on-premises environments. Analyze competitors, develop go-to-market positioning, and grow relationships with cloud providers, ISVs, neoclouds, and open-source communities. Partner with engineering, AI research, silicon architecture, documentation, and developer relations teams to deliver PRDs, deployment blueprints, APIs, SDKs, and validated software offerings.