Teams at Intel

The role involves developing layout design methodologies, integrating full-chip SoC designs, collaborating with various teams, and ensuring scalable solutions for testchip platforms.

Lead and execute ASIC/SoC verification: define verification strategies, develop SystemVerilog/UVM environments, run simulations and formal checks, debug pre-silicon issues, analyze power/performance, collaborate with architects and RTL teams, improve verification methodologies, and mentor junior engineers.

Lead emulation and FPGA modeling from RTL through synthesis and partitioning to enable presilicon verification and software development. Develop, integrate, test, and debug hardware/software in simulation, emulation, and FPGA models; create tools and automation to improve emulation efficiency; optimize performance and debug failing RTL tests; collaborate with cross-functional teams and mentor engineering leaders.