Teams at K2 Space Corporation

Lead ASIC package architecture and detailed FC-BGA/MCM package designs for high-pin-count, high-speed, power-dense SoCs. Drive package trade studies (SI/PI, thermal, manufacturability, reliability), define standards, collaborate with silicon/RF/systems teams, work with OSATs and substrate vendors, and support qualification and production ramp.

Lead end-to-end RTL-to-GDSII physical design for high-performance SoCs in advanced FinFET nodes. Own synthesis, floorplanning, P&R, CTS, STA, DRC/LVS and sign-off; develop methodologies and automation to optimize PPA; drive timing closure, coordinate package/SI/PI and DFT, manage external PD partners and EDA tool flows, and support post-silicon bring-up and production for spaceflight-qualified designs.

Lead full physical design flow for complex SoC blocks and top-level integration from synthesis to GDSII. Drive timing closure, PPA optimization, physical sign-off (DRC/LVS, IR drop, EM), ECOs and tapeout. Collaborate with front-end, verification, DFT, packaging teams and external vendors, develop automation and methodology, and support products through production and spaceflight.