Jobs at Marvell Technology

Leads Marvell’s global trade compliance team across export controls, sanctions, imports, customs, classification, and trade facilitation. Architects scalable compliance systems and processes, oversees investigations and audits, manages metrics and corrective actions, supports M&A, partners with counsel on licensing and regulatory matters, and implements automation including AI tools. The role develops a global team, delivers training, collaborates across business functions, and travels internationally to support stakeholders and process improvements.

Supports digital IC design and implementation for high-performance semiconductor products. Develops and verifies RTL blocks, performs synthesis, static timing and power analysis, debugs designs, explores design methodologies, and collaborates with architecture, verification, and physical design teams. The intern contributes to real chip design efforts involving cloud, AI, storage, networking, and high-speed connectivity applications.

Design and verify high-performance RTL blocks for digital ICs, including synthesis, static timing analysis, timing signoff, power analysis, and debugging. Interns collaborate with architecture, design verification, and physical design teams on ASIC and SoC projects, investigate design methodologies, and contribute to real semiconductor products for cloud, AI, storage, and networking applications.

Leads the enterprise application strategy, roadmap, implementation, and operations for Legal, Compliance, Facilities, Workplace, and Physical Security functions. Oversees CLM, matter management, compliance, IWMS, and facilities platforms; manages integrations, vendors, contracts, SLAs, KPIs, governance, and complex cross-functional delivery. Partners with senior stakeholders and executive leaders to improve workflows, compliance, automation, and adoption across the organization.

Ph.D. interns apply machine learning and AI to semiconductor chip design or enterprise engineering tools. Responsibilities include developing ML models for EDA automation, placement, timing, power, and verification, or deploying LLM, RAG, and agentic systems. Interns will train, evaluate, and deploy models, conduct rigorous experiments, collaborate with engineering and technology stakeholders, assess production performance and safety, and present findings to leadership. The role requires doctoral research in AI, machine learning, computer science, electrical engineering, data science, or a related field.

Ph.D. interns design, simulate, characterize, and validate silicon photonics components, optical engines, and DSP algorithms for PAM4 and coherent optical transceivers. Responsibilities include optical system modeling, link budget analysis, lab testing, silicon bring-up, and collaboration with analog IC, packaging, and systems engineering teams. Interns present research findings and design results while contributing to production-scale optical communications solutions.

Design Verification Interns will develop simulation environments, automated tests, and testbenches for semiconductor processors and SoCs. Responsibilities include analyzing coverage metrics, debugging failed simulations and hardware/software interactions, verifying RTL integration, and collaborating with architects and designers. The role provides hands-on experience with pre-silicon verification, UVM methodology, and industry-standard EDA tools across cloud, AI, storage, and networking chip designs.

Intern will perform synthesis, floorplanning, place and route, clock insertion, timing analysis, and timing closure for complex ASIC and processor logic blocks. Responsibilities include scripting in Python, TCL, Perl, and Shell; debugging design violations with EDA tools; and collaborating with RTL, synthesis, and design teams to resolve congestion and timing bottlenecks. The role supports designs meeting performance, power, and area requirements.

Design verification intern supporting semiconductor processor and ASIC verification. Responsibilities include developing simulation environments, creating automated tests, debugging hardware and software interactions, analyzing coverage metrics, troubleshooting failures, and collaborating with architects and designers. The role involves pre-silicon emulation, UVM testbench development, RTL integration, and verification of block, cluster, and full-chip designs.

Support physical design of ASIC and processor logic blocks through synthesis, floorplanning, place and route, clock insertion, timing analysis, and timing closure. Write scripts in Python, TCL, Perl, and Shell, use industry-standard EDA tools, debug design violations, and collaborate with RTL, synthesis, and design teams to resolve congestion and timing issues.

Lead physical design methodology and automation for next-generation processor and ASIC chips. Provide technical leadership across RTL-to-GDSII implementation, synthesis, floorplanning, place and route, clock tree synthesis, timing closure, power and signal integrity analysis. Collaborate globally with RTL, verification, CAD, and EDA vendors; evaluate tools, influence technical roadmaps, resolve complex implementation issues, and mentor engineers.

Lead physical design and methodology for complex processor and ASIC chips. Drive RTL-to-GDS implementation, multi-voltage place-and-route, static timing, physical verification, integration, and design closure. Collaborate with digital, RTL, and analog teams, while providing technical direction and mentoring. Develop Shell, Python, and Tcl automation scripts to improve design productivity and robustness.

Support Marvell's global export compliance program with product, software, and technology classification under U.S. and international export and customs regulations. Manage visitor and deemed export processes, support trade due diligence, maintain SOPs and training, prepare classification requests and license applications, and collaborate with engineering, operations, and global teams on compliance projects.

Lead global travel and corporate card program operations, vendor relationships, policy, analytics, and T&E transformation. Drive platform selection, automation, compliance, employee experience, and close partnership with Accounting to ensure accurate reconciliations and audit readiness.