Jobs at Marvell Technology

Lead implementation of DFT/Test for complex ASIC/SoC and chiplet designs using Tessent and related EDA tools. Define DFT architecture, run insertion flows, generate patterns, support STA constraints, and drive post-silicon bring-up and debug. Mentor a small DFT team and enhance methodologies and tools across multi-die custom compute designs.

Integrate and manage 3rd-party memory interface IP (DDR/LPDDR/GDDR/HBM/eMMC) across SoC development: define requirements, validate providers, oversee core development and compliance, support core integration, lead test and silicon validation, assist sales and manage supplier issues and reviews.

The Senior Staff Engineer designs and maintains scalable build flows for digital IC designs, improving performance and developer productivity, and collaborates with multiple teams to enhance quality and efficiency.

Design and develop high-speed IC packages focusing on signal and power integrity. Perform electrical design, 2D/3D EM modeling, measurements (VNA/TDR), and package/PCB characterization. Interface with suppliers, IC designers, and cross-functional teams to ensure manufacturability, reliability, and cost targets. Automate SI/PI workflows and contribute to new package technology development.

Support Marvell's global export compliance program with product, software, and technology classification under U.S. and international export and customs regulations. Manage visitor and deemed export processes, support trade due diligence, maintain SOPs and training, prepare classification requests and license applications, and collaborate with engineering, operations, and global teams on compliance projects.

Lead advanced packaging technology roadmap and development for high-performance AI/HPC and networking products. Define package architecture, chiplet topology, PDN and thermal strategies; run signal/power integrity and EM simulations; partner with silicon teams, OSATs and foundries; drive manufacturability, qualification, and volume readiness while creating IP and proof-of-concept technologies.

Lead product management for custom hyperscale silicon targeting AI/data center customers. Own roadmap, customer engagement from exploration to volume production, market and competitive analysis, business planning, collateral, cross-functional execution, and drive design wins with hyperscalers and global sales.

Lead development and automation of physical verification CAD/EDA flows (DRC/LVS) and runsets using Calibre and ICV. Integrate and maintain EDA toolchains, support tape-outs and foundry interfaces, debug verification issues, create validation tests and documentation, and provide technical guidance and training across design teams.

Drive development, deployment, and support of ASIC CAD flow and infrastructure. Build and maintain automation frameworks, flow orchestration, dashboards, and analytics. Integrate standard-cell libraries, memory macros and IP across flows. Define synthesis and physical implementation best practices and collaborate with Design, Physical Design, and IT to improve productivity and quality.

Develop and maintain advanced place-and-route (P&R) flows for advanced nodes, deploy and support flows, integrate into the CAD platform, enable new technologies, interface with EDA vendors, and centralize P&R methodology and knowledge across design teams.

Lead development and maintenance of P&R flows and add-on CAD tools for advanced-node SoC designs. Deploy and support flows, integrate with CAD platform, debug timing/floorplan/power issues, interface with EDA vendors, and innovate solutions for design challenges while keeping up with process and tool evolution.

Lead global travel and corporate card program operations, vendor relationships, policy, analytics, and T&E transformation. Drive platform selection, automation, compliance, employee experience, and close partnership with Accounting to ensure accurate reconciliations and audit readiness.