Teams at Marvell Technology

Lead implementation of DFT/Test for complex ASIC/SoC and chiplet designs using Tessent and related EDA tools. Define DFT architecture, run insertion flows, generate patterns, support STA constraints, and drive post-silicon bring-up and debug. Mentor a small DFT team and enhance methodologies and tools across multi-die custom compute designs.

Integrate and manage 3rd-party memory interface IP (DDR/LPDDR/GDDR/HBM/eMMC) across SoC development: define requirements, validate providers, oversee core development and compliance, support core integration, lead test and silicon validation, assist sales and manage supplier issues and reviews.

The Senior Staff Engineer designs and maintains scalable build flows for digital IC designs, improving performance and developer productivity, and collaborates with multiple teams to enhance quality and efficiency.