Jobs at NXP Semiconductors

Design and implement cost-effective test methods for IP on advanced-node SOC microprocessors. Support characterization, qualification, production test, and debug; develop diagnostic programs; collaborate with design and verification teams pre-tapeout; understand high-speed ATE hardware and semiconductor manufacturing test economics.

Design, develop, and test SoC semiconductor products across process technologies. Optimize device-to-architecture, perform hardware/software co-design, research energy-reduction techniques, prototype system solutions, and collaborate on performance and thermal system-level analysis.

Develop and execute go-to-market strategies for ISEM Power & Energy products (energy storage, management, EVSE, metering). Define market requirements and business cases, create messaging and launch plans, build partner and customer ecosystems, coordinate global cross-unit activities, and support sales/engineering engagement. Travel ~20% for customer visits and events.

Develop and execute digital verification plans, UVM testbenches, test cases and VIP for IP/subsystem/SoC. Perform functional simulation, silicon debug, coverage analysis, automation and lab-based digital validation. Collaborate with architecture, systems, design and cross-functional teams to support product release.

Design, develop, and test semiconductor products and devices. Define test plans and develop automated test programs on ATE, characterize and debug new silicon, validate bench tests, implement design-for-test concepts, support production ramps, and lead yield and cost-reduction test solutions.

Design, develop, test, and document embedded software and system-level solutions for semiconductor applications. Integrate microcontrollers/processors, optimize performance and power, support customers, prepare technical materials, and perform feasibility and benchmark studies. Travel for business meetings and training (~15%).

Design, develop, and deploy data-driven solutions across product lifecycle. Partner with design, manufacturing, test, and quality teams. Mine and analyze company data, build custom models and algorithms, monitor model performance, and propose continuous improvement strategies. Integrate with vendor software and support product modifications and maintenance.

Perform operations research and business analytics to build and maintain enterprise reporting and analytics platforms. Translate business requirements into technical solutions, document requirements and designs, coordinate with developers on design and testing, and deliver dashboards, reports, and data-driven solutions for internal users and executives.

Perform semiconductor reliability engineering for product design, development, testing, and NPI. Develop reporting methods, metrics, and recommended solutions. Ensure quality and reliability procedures are followed, support cross-functional teams and subject matter experts, and apply statistical and lean manufacturing methods to improve processes. Occasional international travel for NPI/NTI activities.

Develop and execute digital verification plans, UVM testbenches, and verification IP for IP/subsystem/SoC. Run simulations, coverage and regressions; debug silicon, automate reports, and collaborate across teams to support product release.

Perform semiconductor physical design, development, and testing. Implement chip layout, DRC, RTL-to-GDS flows, STA, PnR, and optimize clock QoR. Use CAE tools and scripting (Python, Tcl, Perl). Collaborate on design status, testing, failure analysis, and monitor production for conformance to specifications.

Lead development of low-level firmware for semiconductor products, coordinate HW/SW teams, design and validate firmware solutions, establish best practices, support IP usage and debugging, and ensure cross-version compatibility. Occasional international travel (~5%).

Develop and execute digital verification plans, UVM testbenches, test cases, and verification IP for IP/subsystem/SoC. Run simulations, coverage and regressions, debug silicon, automate reports, and collaborate across teams to meet product release requirements.

Perform digital/IP verification for semiconductor products: write verification plans, develop UVM SystemVerilog testbench components, SVA properties, run and debug RTL simulations, collect/analyze coverage, and perform assertion-based formal verification. Maintain verification environment scripts and makefiles.

Design, develop, and test semiconductor devices and chip layouts. Implement RTL-to-GDSII flows, perform static timing analysis, timing closure, PnR, CTS, and failure analysis. Use EDA tools to ensure designs meet specifications and collaborate with customers and teams on testing, production monitoring, and redesign for yield and compliance.

Design, develop, and test semiconductor IP: review microarchitecture, implement RTL, run LEC/Lint/CDC/STA/DFT checks, collaborate with verification to achieve full coverage, track metrics, and deliver RTL with quality signoff.

Perform RTL design, emulation delivery, and SoC verification for semiconductor products. Drive accelerated verification, debug complex SOC issues, improve emulation methodology, enable emulation models, and collaborate with R&D and EDA vendors to ensure high-quality, zero-defect chips.

Develop and execute RTL and IP verification strategies for memory controllers (including MRAM), build and maintain UVM testbenches, write assertions and coverage bins, debug waveforms, perform gate-level simulations, analyze coverage and add tests to close gaps, and support delivery of verified memory IP to SoC teams.

Develop and deploy machine learning and AI solutions for high-volume semiconductor wafer manufacturing. Integrate quality, engineering, production, and support teams to detect and prevent incidents, model large multi-source datasets, collaborate with SMEs, and contribute to global factory standardization and analytics improvements.

Design CMOS SRAM and ROM circuits and periphery to meet compiler performance, power, and area targets. Create and run simulation characterization and testbenches, work with layout and CAD teams, ensure frontend model alignment, and collaborate globally to share methodologies and implement GenAI/EDA efficiencies.