Jobs at NXP Semiconductors

Develop functional safety platforms and IP for automotive and industrial SoCs compliant with ISO 26262 and IEC 61508. Define safety requirements, manage SEooC modules throughout their lifecycle, prepare modules for safety assessments, support SoC integration, and perform FMEDA, FTA, DFA, and fault-injection analyses. Collaborate with design and IP teams, lead safety development across lifecycle phases, report compliance gaps, and contribute to functional safety processes and roadmaps.

Manage IT projects in lead management and marketing automation, coordinating business, IT, development, testing, deployment, and release teams. Gather requirements, create functional designs and workflows, assess solution options, mitigate risks, track delivery, and communicate project status. Partner with Marketing, Sales, architects, vendors, and geographically dispersed teams to improve customer engagement and demand-to-opportunity processes using automation, AI/ML, and Agile practices.

Leads end-to-end new product introduction programs from concept through production ramp. Coordinates engineering, manufacturing, supply chain, quality, and finance teams; manages schedules, budgets, risks, resources, supplier and factory readiness, validation, and executive reporting. Ensures products launch on time, within cost, and at target quality while improving manufacturability, yield, cycle time, and production performance.

Serve as a technical expert for NXP i.MX processors, DDR memory, and embedded system architecture. Support customers through design-in, board bring-up, production ramp, and system-level debugging. Analyze memory controller and PHY behavior, perform validation and root-cause analysis, conduct architecture and design reviews, and develop reference materials. Collaborate with memory suppliers, architects, software teams, and strategic customers to influence future processor and memory subsystem roadmaps.

Secure AI-powered applications, APIs, GenAI solutions, and RAG systems through architecture reviews, application security assessments, penetration testing, secure coding, and implementation of authentication, authorization, data protection, and AI-specific security controls. Collaborate with application, AI engineering, enterprise security, and architecture teams to address risks such as prompt injection, insecure outputs, data leakage, insecure plugins, and retrieval poisoning.

Secure agentic AI systems, autonomous workflows, orchestration frameworks, MCP integrations, APIs, and AI-driven tool execution environments. Responsibilities include designing runtime controls, monitoring agent behavior, validating actions, tracing executions, assessing risks, and implementing guardrails against prompt injection, unsafe tool execution, memory poisoning, and unauthorized actions. The role collaborates with security, AI, platform, DevOps, and enterprise architecture teams while applying OWASP, MITRE ATLAS, and NIST AI RMF practices.

Secure enterprise AI, ML, GenAI, and agentic AI systems through risk assessments, threat modeling, runtime controls, security testing, monitoring, and development guardrails. Evaluate risks such as prompt injection, data leakage, unsafe tool execution, retrieval poisoning, and model abuse. Collaborate with engineering, cloud, application security, architecture, and business teams on secure deployments, AI governance, compliance, remediation, and secure use of AI development tools.

Own end-to-end static timing analysis and timing constraints for advanced-node SoCs, from synthesis through final signoff. Responsibilities include constraint validation, timing correlation, path debugging, timing closure, automated and manual ECO generation, and collaboration with frontend, IP, DFT, implementation, and full-chip STA teams. The role also contributes to methodology improvements, post-silicon bring-up, yield improvement, and production ramp activities.

Own end-to-end verification for complex, safety-critical automotive SoCs, including planning, SystemVerilog/UVM testbench development, simulation, debug, coverage closure, and sign-off. Verify ARM subsystems, interconnects, memory, connectivity, security, boot, low-power, clock/reset, and functional-safety mechanisms. Collaborate with architecture, design, firmware, validation, and safety teams, while supporting post-silicon debug, customer issues, technical initiatives, and engineer mentoring.

Leads legal strategy and execution for mergers, acquisitions, and corporate development transactions. Advises executives, drafts and negotiates transaction documents, manages cross-functional teams and outside counsel, oversees transaction risks and budgets, and supports activities from initial evaluation through closing and integration. Builds repeatable internal processes, coordinates work across jurisdictions, and provides practical guidance on corporate law, governance, antitrust, CFIUS, foreign investment, securities, and disclosure matters.

Supports design-for-test development for microprocessor-based SoCs from test requirements through production. Responsibilities include creating and debugging structural test patterns, pre- and post-silicon verification, ATE pattern conversion, built-in self-test implementation, test coverage analysis, and collaboration with Test Engineering, Product Engineering, and fabrication teams.

Supports the design, administration, implementation, and compliance of U.S. and Canadian employee benefits programs, including health, welfare, retirement, leave, wellness, and enrollment programs. Manages benefits data and functionality in Workday, reconciles billing, audits records, supports vendor and carrier relationships, maintains benefits communications, produces reports, and assists with compliance, market surveys, and open enrollment. Provides customer service to employees and managers while protecting confidential information.

Owns end-to-end static timing analysis and timing constraints for advanced-node SoCs, from synthesis through final signoff. Responsibilities include timing correlation, path debugging, timing closure, automated and manual ECO generation, constraint validation, and collaboration with frontend, IP, DFT, implementation, and full-chip STA teams. The role also supports methodology improvements, post-silicon bring-up, yield improvement, and production ramp activities.

Own end-to-end SoC timing constraints and static timing analysis from synthesis through signoff. Responsibilities include timing correlation, path debugging, timing closure, automated and manual ECO generation, constraint validation, and collaboration with frontend, IP, DFT, implementation, and full-chip STA teams. The role also supports methodology improvements, post-silicon bring-up, yield improvement, and production ramp activities for advanced-node semiconductor products.

Lead the multi-generational roadmap, product definition, business cases, competitive strategy, customer sampling, and lifecycle management for NXP’s edge NPU hardware portfolio. Define silicon specifications, chiplet architectures, SoC integration requirements, and make-versus-buy decisions while coordinating architecture, engineering, software, sales, marketing, customers, and executives. Drive design wins, demonstrations, product ramp, sustaining activities, and end-of-life transitions across AI inference hardware generations.

Owns the product strategy and roadmap for NXP’s edge NPU software stack, including compilers, runtimes, SDKs, developer APIs, model optimization, eIQ integration, and developer experience. The role drives AI framework and open-source partnerships, model support, benchmarking, beta programs, software lifecycle policies, GTM enablement, and system-level demonstrations. It requires strong AI product management experience, compiler and inference pipeline expertise, ecosystem strategy, and familiarity with edge accelerator software.

Design CMOS SRAM and ROM circuits and periphery to meet compiler performance, power, and area targets. Create and run simulation characterization and testbenches, work with layout and CAD teams, ensure frontend model alignment, and collaborate globally to share methodologies and implement GenAI/EDA efficiencies.

Leads a global applications engineering organization responsible for the automotive microprocessor customer journey from evaluation through deployment. Defines customer and developer experience strategy, aligns engineering, product, sales, and executive teams, translates customer insights into engineering priorities, and manages complex technical escalations. Drives transformation in software enablement, developer experience, and AI-powered engineering while balancing customer value, technical investment, scalability, and business outcomes.

Own end-to-end physical design for advanced SoCs, from RTL through GDSII and silicon delivery. Lead floorplanning, synthesis, place and route, CTS, routing, timing, power, physical verification, and signoff while meeting PPA targets. Drive methodology, automation, advanced-node implementation, team mentoring, cross-functional collaboration, EDA vendor engagement, post-silicon bring-up, yield improvement, and production ramp activities.

Architect and develop system management firmware for NXP i.MX SoCs and development boards. Port firmware to new hardware, integrate it across bootloader, trusted firmware, Linux, and MCU SDK components, and develop tests for coverage and performance. Collaborate with architecture, BSP, and support teams to debug and optimize customer systems. Produce documentation and support materials.