Teams at Positron AI

Lead the microarchitecture, SystemVerilog RTL design, integration, optimization, and signoff of complex ASIC and SoC IP for AI inference hardware. Own PPA targets, interfaces, memory integration, verification collaboration, DFT, CDC/RDC, synthesis, timing closure, and post-silicon support. Establish design methodologies, mentor engineers, lead technical reviews, and drive cross-functional architectural decisions.

Lead the architecture, design, verification, physical implementation, tape-out, validation, and production ramp of high-performance AI inference ASICs. Drive PPA optimization, memory subsystem design, hardware/software co-design, and relationships with foundries, IP vendors, and EDA providers. Recruit and mentor the ASIC team while shaping the company’s silicon roadmap and execution methodology.

Owns synthesis methodology, timing closure, constraint development, QoR optimization, and implementation readiness for advanced AI accelerator ASICs. The role transforms RTL into implementation-ready netlists, leads physical-aware optimization and timing budgeting, collaborates across architecture, verification, DFT, and backend teams, and provides technical leadership to external implementation partners. Responsibilities also include developing Tcl and Python automation and applying AI to improve timing analysis, regression, debugging, and engineering workflows.