Jobs at Retym

The Analog Design Engineer will develop high-end ADC/DAC systems for optical communication, focusing on design and verification of complex analog circuits in advanced processes.

Lead and manage a team of verification engineers, define verification strategies, oversee development of environments, and foster technical excellence.

Design and implement VLSI communication systems, collaborating on micro-architecture, RTL coding, verification and debugging while optimizing performance and documenting designs.

Develop and maintain a Linux-based chip management application, implement testing frameworks, optimize processes, and collaborate with international teams in embedded software engineering.

Develop high-end ADC/DAC in advanced processes for optical communication, requiring expertise in layout design and Cadence tools. Teamwork and understanding of schematic flow are essential.

Develop verification strategies for mixed-signal designs, create behavioral models, write and debug testbenches, and run simulations to ensure model accuracy.

The Engineering Site Manager will establish and lead the Austin engineering site, overseeing operations, mentoring teams, and driving technical execution in collaboration with global teams.

Lead RTL design verification efforts, manage test bench architecture, and mentor team members. Requires extensive experience in VLSI verification and digital design blocks.

The DFT Tech Lead will define and implement advanced DFT methodologies for complex chips, focusing on DFT strategy, architecture, and debug specifications.

The role involves developing verification strategies for mixed-signal designs, creating behavioral models, and debugging testbenches using UVM and SystemVerilog for high-speed communication technology.

Responsible for end-to-end verification of RTL designs, leading test bench architecture, mentoring engineers, and ensuring full functionality through detailed coverage analysis.

The DFT Engineer will define and implement DFT methodologies for complex digital chips, debug DFT features, and validate silicon tests.

Develop, maintain, and optimize high-performance SystemC/TLM models for ASIC and optical systems. Translate DSP algorithms from MATLAB to SystemC, create executable reference models, integrate models into mixed-language verification flows, collaborate with architecture/RTL/verification teams, and support system-level debugging and performance analysis.

The Senior Embedded SW Engineer will lead DSP firmware development, provide technical guidance, and collaborate with cross-functional teams to drive project success.