Jobs at Tenstorrent Inc.

The role involves CPU core verification for out-of-order RISC-V CPUs, requiring in-depth microarchitecture knowledge and development/debugging of functional verification models.

Drive top-level implementation of complex AI and CPU SoC designs, ensuring design closure and optimizing chip-level implementations for power, performance, and area.

The Design for Test Engineer will implement DFT features in RTL, analyze test coverage, and support silicon bring-up for advanced AI/ML architectures.

Develop and optimize distributed software systems for AI and HPC clusters, focusing on inter-node communication and scalable architectures.

Lead the development of CPU core-level test generators for RISC-V processors, overseeing validation strategies and guiding a small team while staying hands-on with implementation.

The Timing Engineer will perform static timing analysis, optimizing paths and constraints to ensure chip performance while collaborating with various engineering teams.

Lead EM and IR-drop simulations ensuring robust power delivery and signal integrity for high-performance ICs. Collaborate with teams on power grid strategies and support EMIR sign-off across chip hierarchy.

Lead the development of AI compiler tools, enhance performance analysis, collaborate with hardware teams, and mentor engineers to improve compiler tooling.

Develop and maintain infrastructure platforms for AI services, build APIs, manage Kubernetes clusters, and automate workflows using CI/CD practices.

As a Staff Engineer, you will lead the technical efforts in CPU verification, emulation, and debugging, optimizing the emulation infrastructure and workflow for high-performance CPUs, collaborating with teams to ensure fast and effective product development.

As Director, Systems & Solutions, lead the deployment and optimization of AI compute systems, focusing on hardware technologies and customer engagement to enhance performance and usability.

Design, implement, and maintain TT-Fabric, a low-level networking library for distributed AI training/inference. Build scalable communication systems for thousands of processors, optimize protocols, synchronization, and data movement, integrate TT-Fabric APIs with programming models, and help define long-term distributed systems architecture.

As a Staff Design for Test STA Engineer, you will lead the definition and implementation of DFT methodologies and ensure timing closure for AI processors, collaborating with multiple teams to achieve first-pass silicon success.

Define and implement CPU system RTL, integrate multiple cores/clusters and subsystem components, and drive functional, timing, and power convergence. Collaborate with DV, PD, architecture, performance, validation and test teams to optimize power/performance/area, debug RTL across hierarchies and support pre- and post-silicon execution while improving RTL flows and tools.

The engineer will join a CPU design team focusing on performance analysis, verification, and collaboration with architects to deliver efficient CPU designs using RISC-V ISA.

Physical Design Engineers at Tenstorrent are responsible for implementing high-performance AI SoC designs, overseeing the complete implementation flow from synthesis to tapeout and collaborating with cross-functional teams to ensure all design aspects are met.

Responsible for physical design of high-performance CPUs and AI/ML architectures, including implementation from synthesis to tapeout, and collaborating with front-end teams.

The Staff Design Verification Engineer will ensure quality and reliability of digital designs through verification methodologies, defining strategies, and leading teams in validating complex designs.

The AI Subsystems Physical Design Lead is responsible for timing for subsystems in an AI chip, collaborating with RTL designers, and involved in synthesis, place and route, timing analysis, and power optimization.

As a Full-Chip Physical Design Verification Engineer, you will ensure manufacturable silicon by driving full-chip signoff, leading physical verification closure, and collaborating with various teams to achieve successful tapeouts.