Teams at Tenstorrent Inc.

Design and optimize parameterized RTL for high-performance AI hardware. Run synthesis, timing, and power experiments; improve performance, power, and area; enhance RTL tools and infrastructure; and collaborate with architects, designers, and software teams. The role also involves microprocessor architecture, low-level AI kernels, floating-point arithmetic, low-power microarchitecture, and physical-design-aware RTL development.

Drive execution across Compute IP products from concept through end of life by coordinating Product Management, Engineering, Architecture, Technical Program Management, Sales, and partners. Track milestones, dependencies, risks, deliverables, and customer plans; organize critical reviews and meetings; document decisions; maintain aligned plans; and remove blockers through cross-functional coordination. The role requires technical fluency in CPU, AI accelerator, semiconductor IP, and system dependencies.

Architect end-to-end, rack-scale communication systems for AI accelerators, spanning ASICs, packages, PCBs, connectors, cables, optical engines, and fiber. Define 224G+ SerDes architectures, channel budgets, topology, redundancy, signal integrity, power, latency, BER, FEC, thermal, and reliability targets. Lead simulation, lab validation, failure analysis, supplier requirements, cross-functional design reviews, and interconnect technology roadmaps for next-generation AI infrastructure.