RTL/DV - CAD Infrastructure Engineer

Efficient is seeking a  RTL-DV CAD Lead Engineer to own and advance the EDA flow infrastructure that powers our RTL design and  design verification (DV) teams. In this role you will define methodology, build automation, and provide hands-on flow support across the entire pre-silicon development cycle — from RTL synthesis and lint to UVM testbench execution. You will work at the intersection of EDA tool expertise, scripting/infrastructure engineering.

If you enjoy making engineers wildly productive, love root-causing weird build failures, and don’t mind occasionally wrestling with a vendor license server at 2am then this role is for you. Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities

• Help develop CAD flows in close collaboration with  RTL designers for RTL design: lint (Spyglass/Jasper), CDC/RDC analysis, synthesis (Design Compiler/Genus), equivalence checking (Formality/Conformal), and static timing analysis.
• Develop and maintain simulation flows in collaboration with the DV team  for functional verification using leading simulators (VCS, Xcelium, Questa); manage compile, elaborate, and regression infrastructure.
• Define (in collaboration with the RTL/DV leads) RTL coding guidelines, lint rule policies, and waiver management processes.
• Design and implement build/regression automation frameworks using Python, Makefile, Tcl, and shell scripting; integrate with LSF/SLURM job schedulers for farm-efficient execution.
• Build and maintain CI/CD pipelines (Jenkins/GitLab CI) that gate RTL checkins on lint, CDC, and smoke-regression results.
• Help develop coverage collection and closure infrastructure: merge/analyze per-block and SoC-level coverage databases (VCS CM, Xcelium IMC) and publish dashboards to support sign-off decisions.
• Provide scripted infrastructure for test-list management, seed sweeps, and regression triage; reduce manual overhead through automation.
• Establish process for Soft-IP and Hard-IP downloads and versioning with the RTL/PD team,  VIP integration and BFM bring-up in partnership with DV lead.
• Ensure we have the latest tool versions for the complete RTL/DV EDA tool suite. Establish relationships with EDA vendors to stay on top of licenses and ensure we have the appropriate license features and count available at any given time.
• Mentor junior CAD and DV engineers on flow best practices, scripting techniques, and EDA tool usage.

Required Qualifications

• 8+ years of hands-on CAD or DV infrastructure engineering experience in a semiconductor design environment.
• Proven ownership of simulation, lint, CDC  for complex RTL blocks or SoC-level designs.
• Strong scripting proficiency in Python and Tcl; experience with Makefile-based or equivalent build systems..
• Experience with at least two major commercial simulators (VCS, Xcelium, Questa) and/or formal tools (JasperGold, VC Formal, Conformal).
• Familiarity with job schedulers (LSF, SLURM) and version control systems (Git).
• Strong communication skills; ability to translate complex flow issues into actionable guidance for design engineers.

Desired Qualifications & Experience Requirements

• Exposure to power-aware simulation (UPF/CPF) and low-power flow integration.
• Experience with coverage-driven verification (CDV) at the SoC level.
• Prior work with CI/CD systems (Jenkins, GitLab CI) applied to hardware design flows.
• Contributions to internal tool or flow documentation that enabled team-wide adoption.

We offer a competitive salary for this role, generally ranging from $180,000 to $230,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.