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Intel Corp

CPU Physical Design Engineer

Reposted Yesterday
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In-Office
2 Locations
142K-269K Annually
Senior level
In-Office
2 Locations
142K-269K Annually
Senior level
The CPU Physical Design Engineer designs and implements CPU physical layouts, conducts performance verification, and analyzes results to improve microarchitectures.
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Job Details:

Job Description: 

Do Something Wonderful!

Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and have a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Who We Are

The world is transforming - and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower people's digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver solutions for products that impact customers’ lives? If so, come join us to do something wonderful.

Who you are

The role’s responsibilities include but are not limited to:

  • Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.

  • Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.

  • Conduct verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.

  • Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.

  • Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.

  • Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, lowpower synthesizable CPU.

  • Optimizes CPU design to improve product level parameters such as power, frequency, and area.

  • Participates in the development and improvement of physical design methodologies and flow automation.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.  Requirements listed would be obtained through a combination of relevant industry job experience, internship experience, and/or schoolwork/classes/research. 

 

Minimum qualifications:

  •  Bachelors’ degree in Computer/Electrical Engineering or related field with 8+ years of relevant experience

  • -OR- Master Degree in Computer/Electrical Engineering or related field 6+ years of relevant experience

  • -OR- PhD Degree in Computer/Electrical Engineering or related field 5+ years of relevant experience

Must have experience in some or most of the following:

  • Synthesis, Placement (PnR), Routing, CTS (clocks), PostRoute Optimization, Verification and Sign-off, PrimeTime, Timing ECOs

Preferred qualification

  • Strongly prefer individuals who have gone through multiple Tape-in Cycles and contribute as a senior member of the team.

  • Experience in physical design EDA tools, Perl and Tcl Programming, Low power and high performance design principals, familiarity with Verilog and CPU architecture.

          

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, Texas, Austin

Additional Locations:US, Oregon, Hillsboro

Business group:The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.



Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Top Skills

Clock Tree Synthesis
Perl
Placement
Primetime
Routing
Synthesis
Tcl
Verilog

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