Digital ASIC Design Engineer

The Role

We are seeking a highly skilled Digital ASIC Design Engineer to contribute to the design and implementation of digital subsystems for advanced wireless SoCs. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will architect, develop, and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have flown your sub-system in space and developed cutting-edge mixed-signal SoCs.

Responsibilities

• Design, implement, and verify digital blocks for wireless SoCs using SystemVerilog or Verilog.  
• Translate algorithmic and architectural specifications into synthesizable RTL.
• Implement DSP functions such as filtering, FFT/IFFT, or beamforming.
• Convert chip specifications into RTL using internal IPs and external IPs.
• Design and develop RTL for interfaces, power management, clocking, reset, test & debug.
• Partner with analog/mixed-signal teams to define digital-analog interfaces, calibration engines, and control logic.
• Optimize designs for power, performance, and area (PPA) and support timing closure through synthesis and backend collaboration.
• Contribute to block-level integration, synthesis, and timing closure.
• Participate in design reviews, functional verification, and timing closure.
• Participate in chip bring-up and lab validation of complex digital subsystems.  
• Support your product through production and spaceflight.

Required Qualifications 

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 2+ years of hands-on experience in digital ASIC design.
• Proficiency in RTL design (SystemVerilog or Verilog), synthesis, and linting tools. 
• Experience in micro-architecture definition from architecture guideline and model analysis.
• Experience with DFT tools for scan and BIST insertion.
• Solid understanding of SoC design flows including clock/power domain crossing, timing constraints, and formal verification.
• Familiarity with EDA tools for design, simulation, linting, and STA.
• Experience implementing DSP functions in hardware.
• Understanding of digital design best practices including clock domain crossing (CDC), power domain management, and design-for-test (DFT).
• Strong debugging, problem-solving, and communication skills.

Preferred Qualifications 

• Prior experience in wireless SoC development (e.g. cellular, Wi-Fi, satellite, or mmWave systems) and successful tapeouts in advanced design nodes.
• Design experience in datapath, flow control, arbitration, FIFO, DMA, IOMMU, SoC bus architecture, ARM’s AXI/AHB bus architecture & protocols, serial interfaces such as SPI, I3C, UART.
• Familiarity with DSP algorithm modeling (MATLAB, Python, or C++) and converting models into RTL.
• Hands-on experience with lag bring-up and post-silicon debug.
• Knowledge of digital calibration and control of RF/mixed-signal front ends.
• Exposure to hardware-software co-design and embedded process integration.
• Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits:

• Base salary range for this role is $130,000 – $200,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks