Lead Verification Engineer

The demand for new datacenters and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck isn’t about bigger chips or more of them; it means rethinking the fundamental architecture. The industry's current path isn’t going to meet the need, so we took a different approach.

Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.

We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others. We have also been recognized on the EE Times Silicon 100 list for several consecutive years.

Join us and shape the future of computing!

Position Overview:

We are seeking a highly skilled and experienced ASIC Verification Lead to join our engineering team. In this role, you will take ownership of the verification strategy and execution for complex SoCs, ensuring the functional integrity of our silicon through advanced methodologies and automated flows. You will be a key driver in architectural decisions and the evolution of our verification infrastructure.

Location: Austin, TX. Full-time onsite position.

Key Responsibilities:

• Define and execute comprehensive verification plans, including feature extraction, coverage metrics, and tracking mechanisms.

• Architect and develop scalable UVM-based testbenches and constrained-random environments, as well as targeted SystemVerilog C-based testbenches used for HW/SW co-design.

• Integrate and verify SystemC models within the verification flow to support architectural exploration and early software development.

• Maintain and enhance the verification flow using Cadence EDA tools (e.g., Xcelium, JasperGold). Develop CI/CD scripts to automate regressions and improve turnaround time.

• Development of git based CI/CD tools and quality tests using GitHub Actions.

• Verification management: Manage local and external contractors, using coverage and assertion-based metrics.

• Perform functional verification of processor sub-systems using SystemVerilog and C-based directed testing.

• Integrate FPGA platforms (emulation or prototyping) into the verification flow to accelerate software development and system-level validation.

• Lead sign-off activities, including gate-level simulations (GLS) with SDF annotations, Lint, and Clock Domain Crossing (CDC) analysis.

• Drive verification of high-speed protocols, with a focus on PCIe interface logic and protocol compliance.

• Develop and verify AMS and SystemVerilog models for in-house analog designs.

Qualifications:

• 10+ years of industry experience in verification, ideally leading efforts for verification of complex ASICs in a startup environment.

• Mastery of SystemVerilog, SystemC, and expert-level experience with the UVM methodology.

• Proven experience with SystemC for high-level modeling and seamless integration into RTL verification environments.

• Strong C coding skills specifically for ARM and RISC-V architectures to support firmware-driven verification.

• Deep experience with Cadence tool suites and the ability to script (Python, Bash, or Perl) for CI/CD integration and flow automation.

• Technical depth in PCIe protocol verification, including knowledge of clocking architectures and jitter requirements.

• Experience in running, debugging gate-level simulations with timing (SDF), and managing CDC/Lint tools

Preferred Skills:

• Experience with Analog Mixed-Signal (AMS) verification environments and Real Number Modeling (RNM).

• Formal, assertion-based verification experience is highly desirable

• Familiarity with hardware-assisted verification platforms (e.g., Palladium, ZeBu, or HAPS).

This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on a game-changing technology at the intersection of photonics and AI as part of a collaborative and brilliant team. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world.

Join a team that invests in your future and your well-being. At Neurophos, we offer:

• 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.

• Unlimited PTO. No rigid vacation banks, just a focus on delivery.

• 401(k) matching and stock option opportunities to ensure our success is your success.

• Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.

• Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t.