Principal Engineer

Cadence – ASIC Design Verification - Job Description:

*ASIC/Processor Design Verification position

*Own all aspects of block/sub-system design-verification:

*test-plan creation/execution

*test-bench (all components) creation/enhancement/maintenance

*code/functional coverage

* Will be involved/interact with: post silicon validation/bring up/emulation teams

Job Requirements:

* Strong expertise in building test-benches using: System-Verilog, UVM, C/C++
* Strong digital logic fundamentals and understanding

* Experience in functional coverage/code coverage/assertions (SVA) development and closure

* Experience in creating and maintaining *executable* test plans
* Strong debug skills
* Proficient in scripting/automation using any standard scripting language like Python etc.

* Emulation related experience will be a plus
* Excellent verbal and written communication skills and a good team player

The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.