Senior DFT Engineer

The Role 

We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep expertise in memory BIST and TAP controller insertion at RTL, scan insertion and ATPG, and test strategy development across digital and mixed-signal domains. You will play a critical role in ensuring high test coverage, manufacturability, and first-pass silicon success while collaborating closely with design, verification, and physical design teams.  

Responsibilities 

• Define and implement DFT architecture for mixed-signal SoCs, including scan, MBIST, LBIST, and boundary scan. 
• Lead RTL-level DFT insertion, scan chain insertion and optimization, test point insertion, and low-power DFT methodologies. 
• Own ATPG flow development and execution by generating high-quality stuck-at, transition, and path delay test patterns. Drive coverage closure and pattern optimization and debug pattern failure and silicon correlation.  
• Develop and integrate DFT strategies for mixed-signal blocks, including wrapper-based approaches, and analog test interfaces and BIST solutions. 
• Collaborate with RTL, DV, and PD teams to ensure clean DFT integration at RTL and gate-level, and timing and physical constraints alignment (scan reordering, compression, etc.). 
• Drive DFT verification and signoff, including Scan/ATPG coverage metrics, DRC/Lint checks (DFT rule compliance), gate-level simulation and pattern validation. 
• Support bring-up and silicon debug activities by analyzing tester failures, yield issues, and ATPG pattern correlation with silicon behavior. 
• Contribute to methodology development, automation, and flow improvements. 

Qualifications  

• B.S. or M.S. in Electrical Engineering or related field. 
• 7+ years of experience in DFT for complex SoCs. 
• Strong hands-on experience with RTL DFT insertion (scan, compression, test points), and ATPG tools and flows. 
• Deep understanding of scan architectures, compression techniques, fault models (stuck-at, transition, bridging, path delay), coverage analysis and closure strategies. 
• Experience with low-power DFT techniques. 
• Familiarity with mixed-signal integration challenges and test methodologies. 
• Strong debugging skills across RTL, gate-level, and silicon. 

Nice to Have 

• Experience with MBIST/LBIST implementation and memory repair flows. 
• Knowledge of IEEE 1149.x (JTAG/boundary scan) standards. 
• Experience with multi-voltage domain and power-aware DFT. 
• Exposure to physical design impacts on DFT (scan chain reordering, congestion, timing). 
• Scripting experience for automation. 
• Experience in high-speed interfaces (SerDes) or RF/mixed-signal SoCs. 
• Prior involvement in A0 silicon bring-up and yield ramp. 
• Experience working in cross-functional, geographically distributed teams.  

Compensation and Benefits:

• Base salary range for this role is $170,000 – $250,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks