Senior Principal Analog Design Engineer – Power & Clock IP

About onsemi

onsemi (Nasdaq: ON) is a global leader in intelligent power and sensing technologies, driving innovation to build a safer, cleaner, and smarter world. With a strong focus on automotive, industrial, and AI data center markets, we are shaping the future of vehicle electrification, sustainable energy, and advanced automation.

About the Treo Platform

The Treo Platform is a cutting-edge analog and mixed-signal solution built on 65nm Bipolar-CMOS-DMOS (BCD) technology. Supporting voltage ranges from 1–90V and operating temperatures up to 175°C, Treo is engineered for high‑performance automotive, medical, industrial, and AI data‑center applications. Its modular architecture simplifies design, reduces system cost, and accelerates time‑to‑market. All products are manufactured at our 300mm fab in East Fishkill, NY.

About the Role

We are seeking an Analog Design Engineer to contribute to the development of power management and clocking analog IP blocks for Treo‑based SoC platforms. This is a hands‑on individual contributor role reporting to the Analog Design Team Manager. You will be responsible for the detailed design, verification, and delivery of high‑quality analog IP, working closely with cross‑functional partners to enable successful product tape‑out and silicon validation.

Key Responsibilities

• Design, simulate, and verify power management IP including LDOs, DC/DC converters, and charge pumps. • Design and implement clocking circuits such as PLLs, DLLs, oscillators, and clock distribution networks. • Support IP architecture definition by contributing analysis, trade‑off studies, and design proposals. • Execute schematic design, layout guidance, post‑layout extraction, and corner/Monte Carlo analysis to meet specifications. • Deliver validated analog blocks into mixed‑signal and digital‑on‑top subsystems for SoC integration. • Collaborate with digital design, verification, PDK/technology, and validation teams to resolve integration issues. • Participate in lab bring‑up, silicon characterization, and post‑silicon debug in partnership with validation and test engineers. • Document designs, assumptions, and test results to support IP reuse and long‑term platform quality.

Tools, Flows & Quality

• Use industry‑standard schematic capture and SPICE/AMS simulation tools. • Perform PVT, noise, jitter, reliability, EM/IR, and aging analysis as part of design sign‑off. • Follow established design methodologies, review checklists, and quality metrics; suggest incremental improvements where appropriate.

Innovation & Automation

• Apply scripting, automation, or data‑driven techniques to improve design productivity and robustness. • Collaborate with peers and CAD teams to evaluate emerging EDA capabilities, including AI‑assisted design workflows.

Qualifications – Minimum

• 10+ years of experience in analog IC design. • Hands‑on experience designing power management and/or clocking circuits for integrated SoCs. • Solid understanding of device physics, analog architectures, and layout‑dependent effects. • Proficiency with SPICE/AMS simulation, variability analysis, and mixed‑signal co‑simulation. • Ability to work independently on assigned blocks while communicating progress and risks clearly.

Qualifications – Preferred

• Experience with Verilog‑A/AMS/SV RNM modeling or mixed‑signal verification environments. • Exposure to automotive or industrial reliability and functional‑safety requirements. • Interest in AI/ML‑assisted design, automation, or design‑space exploration.

Success Metrics

• On‑time delivery of assigned analog IP blocks meeting performance and quality targets. • First‑pass silicon success for owned blocks with robust PVT coverage. • Effective collaboration with cross‑functional teams and proactive issue resolution. • Clear technical growth and increasing ownership across platform generations.