Senior Verification Engineer – AI SoC Development

Job Details:

Job Description: 

About the Role Intel's AI SoC organization develops cutting-edge products powering next-generation AI applications. As a Senior Verification Engineer, you will play a key role in ensuring the functional correctness and robustness of complex ASIC designs for AI workloads. If you thrive in a fast-paced environment and enjoy solving challenging problems, this is the role for you.

Position Overview You will perform functional logic verification of integrated SoCs to ensure designs meet specifications. This includes defining and developing scalable and reusable block, subsystem, and SoC verification plans, test benches, and verification environments to meet required coverage levels and confirm to microarchitecture specifications.

You'll execute verification plans and define and run emulation and system simulation models to verify designs, analyze power and performance, and uncover bugs. Working in the presilicon environment, you'll replicate, root cause, and debug issues while finding and implementing corrective measures to resolve failing tests.

Collaboration is key as you'll work with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. You'll document test plans and drive technical reviews with design and architecture teams while incorporating security activities within test plans to ensure security coverage.

Additionally, you'll maintain and improve existing functional verification infrastructure and methodology, absorb learning from postsilicon validation quality, update test plans for missing coverages, and proliferate improvements to future products.

Key Responsibilities • Lead digital ASIC verification at block and system level for advanced AI SoCs

• Define and review comprehensive test plans; ensure alignment with design specifications and coverage goals

• Architect and develop SystemVerilog testbench infrastructure (UVM and non-UVM) for functional verification

• Drive execution of test plans, regression runs, and achieve code and functional coverage closure

• Collaborate with design teams to debug issues and ensure timely resolution

• Contribute to pre-silicon verification, chip bring-up, and post-silicon validation

• Mentor junior engineers and establish best practices for verification methodology

You should possess the following professional traits:

• Ability to lead projects, work cross-functionally, and deliver under tight schedules

• Strong communication skills and a collaborative mindset

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science

• 7+ years of experience in ASIC/SoC verification

Preferred Qualifications • Expertise in SystemVerilog and UVM methodology

• Strong understanding of digital design concepts, clock domain crossings, and power management

• Experience with verification of complex SoCs, including CPU subsystems and standard bus protocols (AXI, AHB)

• Familiarity with industry standard EDA tools, including simulators (VCS, Questa, Xcelium), coverage analysis tools, and modern waveform debug environments.

• Scripting skills (Python, Perl, TCL) for automation

Minimum Qualifications • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science

• 7+ years of experience in ASIC/SoC verification

Preferred Qualifications 

• Expertise in SystemVerilog and UVM methodology

• Strong understanding of digital design concepts, clock domain crossings, and power management

• Experience with verification of complex SoCs, including CPU subsystems and standard bus protocols (AXI, AHB)

• Familiarity with industry standard EDA tools, including simulators (VCS, Questa, Xcelium), coverage analysis tools, and modern waveform debug environments.

• Scripting skills (Python, Perl, TCL) for automation

          

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, California, Folsom

Additional Locations:US, California, Santa Clara, US, Oregon, Hillsboro, US, Texas, Austin

Business group:Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $190,610.00-269,100.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.