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TTM Technologies, Inc.

Staff ASIC Design Layout Engineer

Reposted 2 Days Ago
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Remote
Hiring Remotely in USA
Expert/Leader
Remote
Hiring Remotely in USA
Expert/Leader
Oversee the design and layout of ASIC development, including layout architecture and verification using Cadence tools. Ensure compliance with specifications and manage teams.
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TTM Technologies, Inc. – Publicly Traded US Company, NASDAQ (TTMI) – Top-5 Global Printed Circuit Board Manufacturer

About TTM

TTM Technologies, Inc. is a leading global manufacturer of technology products, including mission systems, radio frequency (“RF”) components, RF microwave/microelectronic assemblies, and technologically advanced printed circuit boards (“PCB”s). TTM stands for time-to-market, representing how TTM's time-critical, one-stop design, engineering and manufacturing services enable customers to reduce the time required to develop new products and bring them to market.

Additional information can be found at www.ttm.com

Position Summary:

The primary responsibilities of this job include:  Overseeing definition, design verification, and layout documentation for ASIC development. Determines layout architecture design, analog layout requirements and Place and Route digital layout requirements for new/ongoing ASIC developments. Defines top down layout requirements. Significant experience leading the IC layout development of multidimensional designs involving the layout of complex integrated circuits, entire active devices, components, sub components and entire subsystems.  Utilizes system tools (such as Cadence Virtuoso) for layout, layout verification and place and route.  Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Writes the semiconductor specification for an ASIC and performs lab verifications. Also supports top level layout planning and final layout verification, including experience with release to manufacture (tape-out) procedures.  IC layout responsibilities associated with new product development or internal R&D efforts.  These include process selection, die size calculations, layers requirements and process options. These efforts are key to provide critical information to determine process requirements, projected cost and complexity of products to support customer or internal specifications.  Individual works in a multi-disciplinary team environment and is required to participate in proposal efforts and technical reviews.

Duties and Responsibilities:

  • Understand customer specifications and drawings to assist in proposal and development efforts.
  • Experience estimating timeframe of design/layout efforts.
  • Work independently or within a team environment. Ensure that project schedules are met.
  • Provide training and guidance to interns, co-ops and technicians.
  • Layout specific skill-set:
    • IC Block & Full-Chip Analog/Mixed Signal
    • Floor-planning, Layout, Integration & Verification
    • Cost Analysis Support
    • Cadence Design Systems Tool Suite
    • Virtuoso (Schematic, Layout),
    • PVS, Assura DRC/LVS, QRC Extraction, Voltus Power Analysis
    • Virtuoso Digital Implementation (Encounter/Innovus) P&R
    • Final Signoff & Foundry Tape-out
    • IC Packaging/Test Support

KSAs:

  • Ability to take ideas and concepts and transform them into producible layout from developed designs.
  • Ability to design experiments, analyze the data and conduct structured problem solving.
  • Must possess strong written and verbal communication skills to document technical specifications and furnish design review presentations.
  • Strong working knowledge of circuit simulation tools.
  • Strong interpersonal and leadership skills.
  • Strong time management skills. Ability to multitask and prioritize.
  • Strong computer skills, specifically Excel and PowerPoint.
  • Actively pursues opportunities to expand job-related knowledge.
  • Executes on program plans and priorities, identifies obstacles and issues and communicates to achieve resolution for assigned tasks.
  • Ability to interface with customers and work in a multi-disciplinary team environment.

Education and Experience:

10yrs. Minimum of IC Physical Design Experience

BS or related degree in engineering or a related discipline

#LI-VT1


Compensation and Benefits:

TTM offers a variety of health and well-being benefit programs. Benefit options include medical, dental, vision, 401K, Flexible Spending Account, Health Savings Account, accident benefits, life insurance, disability benefits, paid vacation & holidays. Benefits are available 1st of the month following date of hire.

Compensation for roles at TTM Technologies varies depending on a wide array of factors including but not limited to the specific office location, role, skill set and level of experience. As required by local law, TTM provides a reasonable range of compensation for roles that my be hired in New York, California and Colorado. For California-based roles, compensation ranges are based upon specific physical locations.

Export Statement:
Must comply with TTM Export Control Policies and Procedures and all applicable laws including ITAR, EAR and OFAC including but not limited to: a) being able to identify ITAR product on the manufacturing floor and understand that access to these products and related technical data is restricted to only US Citizens and US Permanent Residents; b) recognition of  Foreign Person visitors by badge differentiation; c) understand and follow authorization procedures for bringing foreign visitors into facilities (VAL); d) understand the Export and ITAR requirements for shipments leaving the US; e) manage vendor approvals for ITAR manufacturing and services.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability or protected veteran status.

Top Skills

Assura Drc/Lvs
Cadence Design Systems Tool Suite
Cadence Virtuoso
Encounter
Innovus
Pvs
Qrc Extraction
Virtuoso Digital Implementation
Voltus Power Analysis

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