Top Engineering Jobs in Austin, TX

Lead and scale the physical implementation organization for ultra-low-power MCU products. Define strategy, build and mentor teams, oversee full-chip and block-level physical design (floorplanning, power planning, CTS, P&R, timing closure, DRC/LVS, EM/IR signoff), collaborate cross-functionally, manage schedules and tape-out readiness, and ensure first-silicon success and manufacturability.

The Sr. Director of Front End Engineering will drive innovation in semiconductor solutions, oversee engineering teams, and ensure project success with customer-centric solutions.

Own end-to-end digital design verification for complex SoCs at block, subsystem, and full-chip levels. Develop UVM/SystemVerilog testbenches, verification plans, constrained-random and directed tests, scoreboards, coverage models, and C/C++ SoC validation libraries. Automate regressions and reporting, debug failures, perform root-cause analysis, and collaborate with architecture, design, and software teams. The role requires managing verification milestones, risks, and deliverables through multiple successful tape-outs.

The Senior Staff SoC Power and Performance Architect role focuses on advancing ultra-low-power semiconductor solutions for AI edge, wearable, medical device, and IoT applications. The position is based onsite five days per week in Austin and appears intended to lead SoC power and performance architecture in collaboration with cross-functional engineering and product teams. Detailed responsibilities and qualifications were not provided in the posting.

Lead and scale Ambiq's silicon validation organization, define post-silicon validation strategy and automation, drive bring-up, characterization, debug, and production correlation, build global teams and lab infrastructure, manage priorities across concurrent programs, and provide technical leadership for complex silicon issues and customer escalations.

Lead software architecture for low-power Edge AI MCUs: define requirements, perform functional allocation, prototype, guide implementation and testing, optimize performance/power, enforce standards, and mentor engineers.

Lead DFT strategy for ultra-low-power SoCs: design and implement scan, boundary scan, MBIST, ATPG and low-power DFT architectures; generate and analyze structural test vectors; run pre/post-layout simulations; collaborate with design, verification, and test teams to optimize coverage, test time, cost, and bring-up test vectors on silicon.

Architect and implement SoC/MCU RTL (Verilog/SystemVerilog), own complex blocks from spec through tapeout, integrate IP and ARM subsystems, collaborate with verification and physical design, resolve LINT/CDC/RDC issues, support FPGA prototyping and silicon bring-up, and mentor junior engineers.

Lead post-silicon validation and optimization of BLE and other wireless radio subsystems. Define validation methodologies, build automation and firmware for RF/PHY characterization, design RF lab hardware/infrastructure, execute RF performance and power tests, debug system-level issues, and mentor engineers to improve wireless performance and production correlation.

Lead post-silicon power validation, characterization, and optimization for ultra-low-power mixed-signal SoCs. Develop validation methodologies, automation frameworks, firmware, and hardware for precision power measurement. Analyze power across modes and workloads, collaborate with cross-functional teams to resolve silicon issues, and mentor engineers while delivering scalable validation infrastructure and lab automation.