Director of Physical Design

This role will be on-site 5 days a week in NW Austin.

Scope  

We seek an accomplished Director of Physical Design to lead and scale our physical implementation organization for next-generation, ultra-low-power microcontroller (MCU) products. This strategic, high-impact leadership role drives the physical design roadmap, ensures world-class PPA (power, performance, area), and delivers robust silicon for high-volume embedded applications. 

You will guide a multidisciplinary team across design methodology, physical implementation, and sign-off, partnering closely with architecture, RTL design, analog/mixed‑signal, verification, and product engineering to bring innovative MCU solutions to market. 

Key Responsibilities 

Leadership & Strategy 

• Define and execute the physical design strategy for low‑power MCU product lines. 
• Build, mentor, and lead a high‑performing global physical design team. 
• Establish best‑in‑class methodologies for low‑power, high‑reliability physical implementation. 
• Drive continuous improvement in design flows, automation, and signoff quality, including the use of AI tools. 

Physical Implementation 

• Oversee full‑chip and block‑level physical design including: 
• Floorplanning 
• Power planning and low‑power architecture implementation 
• Clock tree synthesis (CTS) 
• Place & route (P&R) 
• Timing closure 
• Physical verification (DRC/LVS) 
• EM/IR and reliability sign-off 
• Power analysis 
• Ensure optimal PPA trade-offs tailored for ultra‑low‑power MCU architectures. 

Cross-Functional Collaboration 

• Partner with architecture and RTL teams to influence early design decisions. 
• Work closely with analog/mixed‑signal teams to integrate mixed‑signal IP into SoCs. 
• Collaborate with product engineering and operations to ensure manufacturability and yield. 
• Interface with foundries to align on technology capabilities, PDK updates, and design rules. 

Execution & Delivery 

• Own physical design schedules, resource planning, and risk management. 
• Ensure first‑silicon success through rigorous signoff and validation processes. 
• Drive tape‑out readiness and support post‑silicon debug. 

Qualifications 

Required 

• Bachelor’s or Master's degree in electrical engineering, Computer Engineering, or related field. 
• 15+ years of experience in physical design for complex SoCs, with at least 5 years in leadership roles. 
• Proven track record of delivering multiple chips to production. 
• Deep expertise in: 
• Low power design techniques (UPF, clock gating, multi‑Vt, power gating, DVFS, retention, etc.) 
• Physical design tools (Synopsys, Cadence, Mentor) 
• Advanced process nodes (40nm → 22nm → 12nm and below) 
• Strong understanding of MCU architectures and embedded system constraints. 
• Excellent communication, leadership, and cross-functional collaboration skills. 

Preferred 

• Experience with mixed-signal SoCs and integration of analog IP. 
• Background in high-volume consumer or industrial MCU products. 
• Familiarity with security-focused or safety-certified MCU designs (e.g., ISO 26262). 
• Experience building and scaling distributed engineering teams. 

Must be currently authorized to work in the United States for any employer.