Lead system architecture for next-generation ultra-low-power AI SoCs from concept through production. Define processor, memory, interconnect, clocking, power, accelerator, and hardware/software partitioning strategies while managing power, performance, and area tradeoffs. Develop architecture specifications and models, evaluate IP, guide silicon implementation and validation, collaborate with customers and cross-functional engineering teams, and mentor architecture staff.

Responsible for post-silicon validation and characterization of analog and mixed-signal SoC subsystems. Develop validation plans, automate testing and data analysis, characterize silicon across process, voltage, and temperature, analyze performance, correlate results with simulation and production data, and debug analog, digital, firmware, power, and board-level interactions. The role also supports validation hardware, lab infrastructure, test coverage, yield improvement, and production readiness.

Designs and develops PCB-based evaluation hardware for low-power, ARM-based SoCs. Responsibilities include hardware architecture, schematic and layout design, system bring-up, lab debugging, manufacturing test development, customer hardware reviews, issue resolution, embedded software support, and creation of application notes and hardware design guidelines.