Leads the physical design organization for ultra-low-power MCU products, defining strategy, building global teams, establishing implementation methodologies, and overseeing floorplanning, power planning, CTS, place-and-route, timing closure, physical verification, and reliability sign-off. Partners with architecture, RTL, analog, verification, product engineering, operations, and foundries to optimize PPA, manage schedules and risks, deliver tape-outs, and support post-silicon debug.

Own pre-tapeout quality for digital SoC modules on MCU platforms. Responsibilities include architecture and microarchitecture, Verilog/SystemVerilog RTL development, third-party IP integration, verification and FPGA collaboration, timing and power closure, LINT/CDC/RDC quality checks, silicon bring-up, and validation. The role requires expert-level SoC design knowledge, technical leadership, and the ability to guide programs across technical areas.

Lead development, integration, optimization, and validation of GPU hardware abstraction layers and graphics software stacks for embedded Ambiq MCUs. Responsibilities include OpenGL ES and vector graphics middleware, display integration, UI frameworks, performance and power optimization, example applications, testing, FPGA pre-silicon verification, post-silicon bring-up, and hands-on hardware/software debugging.