Articles about Arm

Serves as a senior technical authority for CPU physical implementation, RTL optimization, and power, performance, and area improvement. Leads Solution Engineering alignment, Cadence EDA strategy, process-node technology porting, implementation-flow enablement, and correlation across teams and partners. Establishes scalable methodologies, qualification models, governance, and diagnostic capabilities while influencing global stakeholders and vendors without direct authority.

Provide technical mentorship and support to partners integrating Arm CPUs and System IP into SoCs. Perform RTL simulation-based debugging, SoC build reviews, deliver training, influence IP development, test IP, and create knowledge-base content and tooling to improve partner outcomes.

Design and implement SystemVerilog RTL for memory controller functional units. Develop specifications and microarchitecture, collaborate with design and verification teams, debug functional and performance issues, and meet performance, power, and area targets. The role requires knowledge of DRAM standards, AMBA bus protocols, RTL design, synthesis, and design-quality checks such as lint and CDC analysis.