Jobs at Arm

Leads global sourcing strategy for semiconductor foundry and ASIC services from product development through high-volume manufacturing. Manages foundry and ASIC supplier relationships, negotiations, capacity reservations, pricing, NRE, masks, and long-term agreements. Builds semiconductor cost models, secures advanced-node capacity, mitigates supply and technology risks, monitors market dynamics, and presents sourcing recommendations to senior leadership. Partners cross-functionally with engineering, product, operations, finance, and supply chain teams.

Leads global sourcing strategy for semiconductor IC test equipment, hardware, and outsourced test services. Manages ATE platforms, OSAT relationships, supplier negotiations, test capacity planning, equipment deployment, capital investments, utilization, and lifecycle management. Partners with engineering and operations teams to support product development, qualification, ramp, and high-volume manufacturing while presenting sourcing strategies, costs, risks, and capacity plans to senior leadership.

Owns component engineering strategy and lifecycle risk management for board-level electronics from architecture and NPI through production and end of life. Responsibilities include component selection, characterization, qualification, alternate-source development, BOM risk analysis, dual-sourcing, obsolescence mitigation, supplier collaboration, reliability support, and component governance. The role partners with Electrical Engineering, Supply Chain, Manufacturing, Quality, suppliers, and contract manufacturers to balance technical performance, reliability, cost, availability, and lifecycle risk.

Lead global sourcing strategy for advanced IC substrates from product development through high-volume manufacturing. Manage strategic supplier relationships, evaluate technology and capacity roadmaps, negotiate pricing and long-term supply agreements, secure manufacturing capacity, mitigate supply risks, develop alternate suppliers, and present sourcing recommendations to senior leadership. Partner cross-functionally with engineering, operations, quality, finance, and supply chain teams to align supplier capabilities, costs, technology, and supply assurance with product roadmaps.

Conduct original robotics research across areas such as robot learning, perception, planning, control, safety, systems, and mechatronics. Develop and implement novel methods on real robots and in simulation, integrate capabilities into intelligent systems, publish research, identify system-level requirements, and collaborate with multidisciplinary researchers and external partners to shape Arm’s robotics technology roadmap.

Conduct original robotics research across learning, perception, planning, control, safety, systems, and mechatronics. Develop and evaluate methods on real robotic platforms and simulations, integrate multidisciplinary capabilities into intelligent systems, publish research, identify system-level bottlenecks, and influence the technical roadmap for future robotics compute and software platforms.

Build and operate scalable platform services and APIs that improve engineering workflows. Develop Kubernetes operators, automate self-service capabilities, provision cloud infrastructure with Terraform, and manage reliable workloads using AWS, Docker, Kubernetes, Helm, and ArgoCD. Lead technical initiatives, apply secure software engineering practices, support production systems, and participate in an on-call rotation while collaborating across engineering teams.

Design and integrate complex compute subsystems and SoCs, including PCIe, DDR, HBM, UCIe, and Ethernet IP. Develop micro-architecture specifications and RTL, perform design checks, debug issues, and collaborate with verification, performance, backend implementation, and project management teams. Support floor planning, timing closure, design methodologies, and team development while guiding other engineers.

Provide technical mentorship and support to partners integrating Arm CPUs and System IP into SoCs. Perform RTL simulation-based debugging, SoC build reviews, deliver training, influence IP development, test IP, and create knowledge-base content and tooling to improve partner outcomes.

Design and implement SystemVerilog RTL for memory controller functional units. Develop specifications and microarchitecture, collaborate with design and verification teams, debug functional and performance issues, and meet performance, power, and area targets. The role requires knowledge of DRAM standards, AMBA bus protocols, RTL design, synthesis, and design-quality checks such as lint and CDC analysis.

Develop and deploy Raven, a C++ dynamic random test generator for Arm CPU verification. Responsibilities include implementing verification functionality, creating test templates for architectural and microarchitectural features, debugging user and QA issues, collaborating with CPU verification engineers, and applying computer architecture specifications. The role requires strong C++ development, assembly programming, computer architecture knowledge, and familiarity with CPU verification environments.

Leads strategic UX research for AI and developer platforms, studying tools, APIs, runtimes, documentation, workflows, and agent-mediated experiences. The researcher identifies high-value questions, applies qualitative and quantitative methods, influences product and platform direction, and translates insights into design principles and recommendations. Responsibilities include engaging developers, customers, and partners; representing user needs in leadership and roadmap discussions; and mentoring peers to improve evidence-based research practices.

Develop cycle-accurate performance models for coherent and non-coherent Arm interconnects. Collaborate with micro-architects, RTL, validation teams, and customers to assess architectural trade-offs, develop features, build performance test suites, identify bottlenecks, and deliver data-driven system performance insights. The role requires strong C++, SystemC TLM, and Python skills, plus expertise in SoC performance modeling and computer architecture.

Design RTL logic for a coherent interconnect fabric using SystemVerilog. Collaborate with verification, implementation, performance, and power teams to deliver high-performance, low-power IP. Track and coordinate tasks, debug functional and performance issues with simulation and tools, and improve design methodology across the System IP group.

Develop and analyze memory controller IP and system performance models for Arm-based SoCs. Optimize power, performance, and microarchitecture using workload analysis, simulation, and emulation. Create performance methodologies, identify system bottlenecks, guide internal teams and partners, correlate models with RTL, and mentor engineers. Requires strong computer architecture expertise, C++ development, scripting, and experience with memory or interconnect performance modeling.

Own end-to-end technical delivery for Arm’s engineering platforms, including requirements, planning, implementation, production support, and on-call incident response. Develop and maintain CI/CD, build, testing, cloud, containerization, infrastructure-as-code, and clustered computing solutions. Improve developer experience through automation, self-service infrastructure, and efficient engineering workflows.

Leads end-to-end product engineering for advanced HPC silicon from pre-silicon readiness through bring-up, qualification, production ramp, and HVM. Owns silicon characterization, performance and power correlation, HSIO validation, manufacturing test, SLT, yield, reliability, failure analysis, and advanced packaging. Partners cross-functionally on productization requirements, risk mitigation, manufacturing readiness, and root-cause resolution. Provides technical leadership, communicates complex issues, establishes product-health metrics, and mentors engineers.

Design and integrate PCIe, CXL, and other IP subsystems for SoCs. Develop micro-architecture specifications and RTL, perform design checks, fix bugs, and collaborate with verification, performance, backend implementation, and project management teams. Support floor planning, constraints, timing closure, and design methodology improvements while guiding team members.

Senior SoC Verification Engineer role at Arm. The provided posting contains salary and company policy information but no detailed responsibilities or qualification requirements.

Architects, implements, and validates design-for-test techniques for Arm SoCs and subsystems. Responsibilities include DFT insertion, RTL and gate-level simulation, ATPG pattern generation, coverage debugging, DFT timing analysis, scan insertion, timing closure, ATE test validation, silicon debug, and characterization. The role collaborates with RTL, verification, physical implementation, test, and product engineering teams throughout development and tape-out.