Jobs at Arm

The Staff DevOps Engineer will enhance the engineering experience at Arm, overseeing technical deliveries and collaborating with teams to improve software and hardware tooling through cloud services and CI/CD practices.

The role is accountable for strategic security leadership across semiconductor engineering environments, guiding teams in security practices while ensuring business efficiency.

Manage full lifecycle recruiting for interns and graduates, partner with hiring managers, maintain ATS data and hiring metrics, support campus events logistics, and ensure inclusive candidate experience.

Lead firmware product strategy and multi-generation roadmap for Arm's AGI CPU family. Engage customers, partners, and engineering to define requirements, prioritize features, and drive delivery for scalable infrastructure deployments. Support go-to-market, represent product strategy, and coordinate cross-functional teams to ensure robust firmware readiness at scale.

Design and define high-speed on-chip interconnect architectures (coherent and non-coherent) including PCIe, CXL, and UA Link for scalable SoCs. Lead roadmap and early customer architecture engagements, collaborate with performance, power, physical design, software and firmware teams, and perform workload analysis and performance modeling to meet compute, memory, and interconnect targets.

Define and evaluate next-generation CPU microarchitectures for Cortex-X and Neoverse, develop performance models and simulations, analyze workloads, estimate performance/power/area trade-offs, collaborate with design teams and partners, and mentor junior engineers.

Customer-facing technical lead for platform firmware bring-up and debug across silicon, firmware, and OS layers. Support reference and custom platforms, debug DDR/PCIe and multi-socket issues, drive triage and root-cause analysis with internal teams, deliver workshops and documentation, and enable partners to accelerate platform readiness.

Manage and advance internal server lab and compute infrastructure: hardware board bring-up, lab IT and networking, CI/CD (GitLab) reliability, provisioning automation, MAAS administration, backup/recovery, co-lo logistics, cloud zone maintenance, security escalations, procurement coordination, documentation, and platform enablement support.

Lead end-to-end ATE secure provisioning for semiconductor manufacturing: define and implement fuse programming and lifecycle transitions, develop/validate Advantest 93K test methods, ensure secure boot and device identity, coordinate with Design/DV/Firmware/Security/Manufacturing, and define production controls, traceability, and guardrails across wafer sort, final test, SLT, and HVM.

As a SoC Emulation Engineer, you'll develop verification testbenches, modify RTL for SoC, and collaborate to define future architectures.

Drive hardware-aware ML algorithm development and optimization for ARM compute platforms. Analyze ML workloads (PPA focus), prototype algorithms, and optimize state-of-the-art networks for CPU/GPU/NPU targets.

As a Performance Analysis Engineer, you will analyze SoC performance, identify bottlenecks, collaborate with architects, and develop testing workflows.

Design RTL logic for a coherent interconnect fabric using SystemVerilog. Collaborate with verification, implementation, performance, and power teams to deliver high-performance, low-power IP. Track and coordinate tasks, debug functional and performance issues with simulation and tools, and improve design methodology across the System IP group.

Lead architecture, design, and delivery of coherent and non-coherent SoC interconnect fabrics. Define topology, QoS, latency, bandwidth, and power strategies; drive performance modeling, RTL microarchitecture and verification, debug system-level issues, mentor engineers, and plan interconnect roadmaps while collaborating with CPU/GPU/NPU/memory teams.

Lead sub-system level verification of high-speed IOs (PCIe/CXL) including test plan creation, SystemVerilog/Verilog/UVM testbench and test development, simulation and emulation, performance and interoperability verification, debugging failures, improving verification methodology, and mentoring junior engineers while collaborating with architects, RTL designers, and cross-functional teams.

Develop and execute verification plans and testbenches (UVM/SystemVerilog/C) for Security IP and embedded processor subsystems. Verify cryptography, secure boot, key management, and multi-clock/multi-power domain IP; debug failures, improve verification methodology, and mentor teammates toward product sign-off.

Lead end-to-end delivery of an Arm AGI SoC program from pre-silicon through commercialization. Maintain integrated program plans, drive cross-functional decisions, report status to senior leaders, align engineering/product/operations, identify risks and execute recovery plans, and ensure firmware, software, validation, and customer readiness for deployment.

Design and productize Hardware Security IP and subsystems for SoCs. Develop architectures, RTL, constraints; drive verification, debug, optimization, and sign-off. Mentor teammates and contribute to roadmaps, processes, and cross-team collaboration.

Lead full-cycle recruitment for technical and non-technical roles in Austin, partnering with hiring managers to build pipelines, source passive and active candidates, influence hiring decisions, and deliver inclusive candidate experiences. Drive employer branding, data-driven reporting, market insights, and offer strategy to meet hiring goals and support growth.

The role involves managing safety and cybersecurity for automotive SoC programs, ensuring compliance with standards, and improving development processes.