Jobs at Arm

Develop and analyze machine learning workloads, prototype hardware-aware algorithms, and create tools supporting performance, power, and area optimization on current and future ARM platforms. The role involves ML model optimization, hardware-software co-design, architecture exploration, and large-scale deep learning model training using Python, TensorFlow, PyTorch, and GPU systems.

Manage functional safety and cybersecurity compliance for automotive and robotics SoC programs. Develop scalable approaches for ISO 26262 and ISO/SAE 21434, align engineering practices with standards, prepare teams for external assessments, conduct audits, manage compliance evidence, and drive process improvements, training, corrective actions, and best practices across complex semiconductor development environments.

Create, maintain, and improve structured technical documentation for Arm System IP technologies. The intern will identify user needs, research technical information, interview domain specialists, and collaborate with architects, engineers, marketers, and other writers. The role focuses on making complex concepts accurate, precise, and accessible to developers, engineers, and partners while gaining experience with technical writing tools and documentation standards.

Develops micro-architecture and RTL for SoC power management, voltage control, clock, and reset IP. Designs power-state transitions and multi-domain control logic while meeting functional, power, performance, area, and timing goals. Performs synthesis, timing analysis, lint, CDC, RDC, and power-aware checks; collaborates with verification and implementation teams on integration and debugging. Contributes to design methodologies, automation, technical reviews, and delivery of semiconductor projects.

Lead cross-functional product engineering for SoC/CPU/GPU manufacturability from pre-silicon readiness through post-silicon bring-up. Own manufacturing flow, ATE/SLT test and correlation, yield improvement, silicon/package reliability qualification, PVTF characterization, and failure analysis while coordinating with foundries, OSATs, design, validation, test, and quality. Support NPI/HVM readiness and audits, with international travel up to 20%.

Build and operate server lab, data center, networking, cloud, and compute infrastructure for server development and validation. Responsibilities include hardware deployment, racking and cabling, Linux administration, networking, CI/CD runner and pipeline management, validation testing, log analysis, backups, recovery, security, incident response, troubleshooting, documentation, and user support. The role is primarily onsite in Austin with occasional travel to offsite colocation facilities.

Leads complex semiconductor and engineering development programs from definition through integration, validation, and delivery. Owns project execution, schedules, dependencies, risks, resources, scope changes, metrics, and recovery plans. Coordinates cross-functional engineering teams and technical leads across disciplines and locations, resolves delivery challenges, influences stakeholders without direct authority, and communicates progress and trade-offs to senior leadership. Projects may involve semiconductor IP, SoCs, FPGAs, emulation platforms, boards, validation, and hardware/software enablement.

Develop verification plans, SystemVerilog/UVM testbenches, constrained-random stimulus, coverage, and regression strategies for Arm's coherent interconnect products. Collaborate with architects and designers to debug features, resolve functional failures, close coverage, and improve verification methodologies. The role requires CPU microarchitecture expertise, including cache coherence, memory systems, and AMBA bus protocols.

Build and operate Arm’s production AI platform infrastructure, including MCP servers, model gateways, runtime services, and control-plane components. Develop scalable, secure, observable, and cost-aware platform patterns using Kubernetes, cloud infrastructure, infrastructure as code, and GitOps. Responsibilities include automation, monitoring, incident response, reliability engineering, secrets and identity management, network controls, auditability, lifecycle management, and participation in an on-call rotation.

This role focuses on enhancing developer experience through improved tools and solutions, collaborating with developers and engineering teams, and managing product roadmaps for performance tooling.

Coordinate third-party IP delivery and lifecycle management across semiconductor programs. Track vendor commitments, procurement readiness, schedules, risks, dependencies, and recovery plans. Partner with engineering, procurement, quality, legal, finance, program management, and suppliers to resolve blockers and support leadership reporting. Improve IP lifecycle processes, reporting tools, and workflows while ensuring delivery and compliance readiness.

Develop and operate software infrastructure supporting Arm CPU design and verification. Build automation for distributed HPC workloads, CI and regression systems, observability, source-control and verification-tool integrations. Diagnose complex issues across software, hardware verification, operating systems, compute, and storage. Improve compute utilization, verification throughput, failure analysis, and engineering workflows while delivering maintainable production-quality software.

Provides independent quality oversight for CPU development across requirements, design, verification, release, and maintenance. Leads quality reviews, defect investigations, root-cause analysis, corrective actions, and errata resolution. Uses quality data and customer feedback to identify trends, improve verification effectiveness, strengthen engineering practices, and simplify development processes. Collaborates with engineering teams and contributes to review boards and cross-team improvement initiatives.

Lead product strategy and lifecycle for Physical IP and CPU products targeting Edge AI. Define roadmaps, translate market and customer insights into engineering requirements, drive competitive positioning, and engage Tier 1 customers to secure design wins. Collaborate cross-functionally with engineering, sales, marketing, and executives to influence CPU roadmap, deliver commercial cases, and ensure customer success.

Leads pre-silicon quality engineering for high-speed I/O subsystems including DDR, PCIe, eUSB, and SerDes. Drives DFX metric closure, validates silicon-to-simulation correlation, analyzes eye diagrams, BER, margining, and BIST data, and develops test automation and visualization scripts. Chairs TPIP councils and collaborates with vendors, architects, integration, validation, package, and SIPI teams to ensure quality across upcoming systems-on-chip.

Develop and maintain SystemVerilog/UVM verification environments for Memory Controller IP. Create verification plans, tests, assertions, coverage models, and scoreboards for LPDDR and DDR technologies. Analyze regressions, simulations, waveforms, and logs to debug RTL, testbench, and protocol issues. Collaborate with architects, RTL designers, and verification teams to achieve coverage closure and sign-off, while improving automation and verification workflows.

Leads and develops a Technical Program Management organization responsible for post-silicon execution across complex Arm-based SoC programs. Oversees silicon validation, bring-up, debug, production readiness, integrated planning, risk management, dependencies, governance, and milestone execution. Partners with hardware, firmware, software, architecture, and external development teams while influencing senior leadership, improving operational rigor, and resolving cross-functional challenges.

Architect high-speed PCIe, CXL, and UA Link interconnect subsystems for scalable Arm-based SoCs. Define technology roadmaps, develop implementation-ready specifications, integrate coherent and non-coherent architectures, and optimize bandwidth, latency, power, and performance. Collaborate with customers and multidisciplinary hardware, software, firmware, physical design, and platform teams while guiding workload analysis, performance modeling, and end-to-end system solutions.

Owns secure semiconductor manufacturing test and provisioning on Advantest 93K ATE. Responsibilities include test architecture, SmarTest program development, first-silicon bring-up, characterization, HSIO and structural test integration, hardware coordination, silicon and ATE debug, production release, OSAT deployment, yield improvement, and high-volume manufacturing readiness.

Leads SoC power analysis, modeling, optimization, and pre- and post-silicon power convergence. Manages and mentors power engineers while collaborating with architecture, design, verification, and product teams. Defines power methodologies, workflows, budgets, and sign-off processes; develops workload scenarios; improves accuracy and silicon correlation; and drives performance-per-watt targets throughout the SoC lifecycle.