Jobs at Cadence Design Systems

Lead Front End Design projects, mentoring RTL engineers, define IP features, write and optimize RTL code, oversee pre-silicon verification, and collaborate with cross-functional teams.

The DevOps Sr Principal Software Engineer will lead infrastructure evolution, implement core systems, collaborate with R&D, and ensure system health and compliance.

Develop and optimize a deep learning compiler stack (using LLVM/MLIR) that lowers neural networks from frameworks (PyTorch/TensorFlow/Caffe) to efficient code for embedded/special-purpose platforms, implement NN operation kernels, create optimization and scheduling strategies for multicore/DSP/accelerators, benchmark performance, and collaborate with hardware designers and partners.

Develop a deep-learning compiler stack that converts neural network descriptions into optimized code for embedded and special-purpose platforms. Implement and optimize NN operations, use LLVM/MLIR, benchmark on DSPs/accelerators, devise multiprocessor partitioning/scheduling, validate runtimes, and collaborate with hardware designers and partners.

Lead Front End Design projects, mentor a team of RTL design engineers, develop microarchitectures, and oversee verification activities in the semiconductor industry.

Lead product and go-to-market strategy for Cadence digital and mixed-signal verification solutions. Partner with strategic accounts to define technical and commercial requirements, influence roadmap and packaging, enable field teams, and drive adoption and revenue across the customer lifecycle from evaluation to enterprise deployment. Lead cross-functional initiatives with Sales, Apps Engineering, and R&D and engage with executives to deliver measurable business outcomes.

Lead development of reliable, scalable C/C++ software tools for DFT/ATPG. Design and optimize algorithms and software architecture, use static/dynamic analysis, Unix/Linux and scripting, collaborate with engineers and customers to deliver high-performance EDA solutions.

Lead product and business growth for Cadence digital and mixed-signal verification solutions by owning customer-facing strategy, market development, and go-to-market. Partner with strategic accounts to uncover technical and commercial pain points, shape product direction and packaging, build value propositions, and drive enterprise adoption. Lead cross-functional initiatives across Sales, Applications Engineering, and R&D, engage executives, and align teams to measurable outcomes across the full customer lifecycle.

As a Senior Principal Application Engineer, you provide technical support for Cadence's Jasper Formal Verification solutions, mentor juniors, and build client relationships while driving innovative formal flows.

Responsible for designing, developing, debugging, and supporting Design-for-Test software in VLSI Design Automation.

The Technical Program Manager will oversee R&D projects and customer engagements, ensuring effective project execution, stakeholder communication, and team collaboration.

Develop, design, troubleshoot, and support Cadence Innovus for digital implementation. Work on placement, routing, optimization, timing and power analysis; collaborate with customers; apply C/C++ on UNIX. ML/GPU knowledge preferred.

As a Software Engineer I, you will provide R&D support, engage in debugging, and develop new features to enhance product performance in a collaborative team environment.

The Lead Solutions Engineer will develop and validate DRC and LVS runsets for Pegasus tools, lead automation frameworks, and provide technical support to customers while mentoring junior engineers and collaborating with R&D.

Lead the development of advanced packaging and 3DIC analysis flows. Requires extensive experience in signal integrity and power integrity related to IC and PCB design, as well as customer interaction. Must have strong knowledge of Cadence tools and advanced packaging concepts.

The Senior Principal Design Engineer supports Cadence product adoption, focusing on ASIC design and methodology improvement, while managing customer evaluations and performing design automation scripting.

Develop bare-metal firmware in C for DDR5 PHY using microcontrollers; implement low-level APIs and training algorithms; collaborate with hardware designers and verification teams for firmware-hardware co-verification; debug in RTL (C+Verilog) simulations and on silicon bring-up; use scripting and EDA tools for verification and diagnostics.

Lead verification projects at subsystem/SOC level, develop testbenches, mentor engineers, and ensure metric-driven quality verification processes.

The Sr IP Sales Executive is responsible for developing and driving a sales pipeline for Design IP technology, managing multi-functional teams, and achieving sales targets through strategic selling and market feedback.

The role involves collaborating with R&D and Application Engineering teams to enhance chip design tools, focusing on PPA benchmarking and optimization.