Jobs at Cadence Design Systems

Lead product and go-to-market strategy for Cadence digital and mixed-signal verification solutions. Partner with strategic accounts to define technical and commercial requirements, influence roadmap and packaging, enable field teams, and drive adoption and revenue across the customer lifecycle from evaluation to enterprise deployment. Lead cross-functional initiatives with Sales, Apps Engineering, and R&D and engage with executives to deliver measurable business outcomes.

Supports AI-enabled market intelligence, competitive analysis, strategic research, and M&A due diligence. The intern will test AI models and workflows, build prompting and RAG solutions, synthesize public research, create market and competitive overviews, prepare executive presentations, and develop strategic recommendations. The role offers exposure to emerging technologies, semiconductor markets, business strategy, and executive decision-making.

Lead and execute complex digital implementation and signoff customer engagements. Provide expert guidance on physical implementation, verification, timing and power analysis, enable advanced-node process platforms, drive PPA realization, develop methodologies and flows, partner with R&D/FAEs/foundries, and manage and mentor a customer-facing engineering group.

Lead SoC/ASIC DFT activities including scan insertion, compression scan, LBIST/MBIST, and ATPG pattern generation. Verify and debug ATPG testbenches and failures, work with synthesis/Verilog testbenches, apply JTAG/IEEE standards, and collaborate across architecture, design, and customers to independently deliver DFT solutions using Cadence flows.

Develop bare-metal firmware in C for DDR5 PHY using microcontrollers; implement low-level APIs and training algorithms; collaborate with hardware designers and verification teams for firmware-hardware co-verification; debug in RTL (C+Verilog) simulations and on silicon bring-up; use scripting and EDA tools for verification and diagnostics.

Develop and validate power integrity and PDN analysis methodologies for digital sign-off. Collaborate with R&D to build AI-driven IR mitigation, 3DIC and electrothermal optimization flows, support strategic customers, and drive multiphysics product engineering and solutions.

Lead verification projects at subsystem/SOC level, develop testbenches, mentor engineers, and ensure metric-driven quality verification processes.

The role involves collaborating with R&D and Application Engineering teams to enhance chip design tools, focusing on PPA benchmarking and optimization.

Lead strategic co-selling, marketing and communications partnerships with Tier 1 ecosystem partners to grow joint business and channels. Develop partner programs, campaigns, events, and collateral; align executives and sales through training; generate qualified leads and product opportunities; nurture long-term relationships; track and report program performance and ROI.

Entry-level, cohort-based rotational role providing front-line EDA application support, technical sales assistance, and design services. Work with customers and internal teams on digital/analog design, verification, simulation, physical design, timing/power/SI sign-off, embedded HW/SW co-verification, and hardware emulation. Two six-month technical rotations followed by placement in a CST business group.

Develop and debug bare-metal C firmware for DDR5 PHY on microcontrollers, collaborate with hardware designers and verification teams to implement training algorithms, perform RTL and silicon bring-up debugging, and use scripting and EDA tools for co-verification and simulation.

Develop and debug bare-metal firmware for DDR5 PHY microcontrollers, collaborate with hardware designers and verification teams to implement training algorithms, perform firmware-hardware co-verification in RTL simulations, and support silicon bring-up and debugging using EDA tools and scripting.

Design-for-Test (DFT) engineer responsible for scan chain and compression insertion, MBIST/LBIST, ATPG pattern generation and verification, debugging failures, verifying ATPG testbenches, and collaborating across architecture, design, and customer teams. Work with JTAG/IEEE test standards and Cadence flows to meet test coverage and quality metrics.

Serve as a technical pre-sales leader, driving cross-functional campaigns that match Cadence digital design and EDA solutions to customer needs. Build relationships with customer engineering and leadership, influence buying decisions, manage complex technical projects, and support multi-million-dollar sales through technical expertise across the RTL-to-GDSII flow and AI/ML optimization methods.

Lead Front End Design projects, mentoring RTL engineers, define IP features, write and optimize RTL code, oversee pre-silicon verification, and collaborate with cross-functional teams.

Lead development of scalable EDA flows and AI/LLM-driven automation for 3DIC, interposer, and RDL systems. Build flow-generation, debugging assistants, root-cause analysis, and platform integration using C++, Tcl, Python, and Java. Collaborate across teams to define requirements, validate behavior, and deliver production-quality, automated workflows improving usability and debug efficiency for complex package and system-level designs.

Lead design of mmWave (30+ GHz) RF transceivers and components across full product lifecycle. Develop PAs, LNAs, mixers, VCOs, PLLs, and Tx/Rx chains; perform parasitic/EM/thermal modeling, layout and verification, tape-out, and lab validation. Engage with customers and use advanced EDA and EM tools on RF SOI processes.

Responsible for designing, developing, debugging, and supporting Design-for-Test software in VLSI Design Automation.

The Technical Program Manager will oversee R&D projects and customer engagements, ensuring effective project execution, stakeholder communication, and team collaboration.

As a Software Engineer I, you will provide R&D support, engage in debugging, and develop new features to enhance product performance in a collaborative team environment.