Jobs at Cadence Design Systems

Entry-level rotational application engineering role for new STEM bachelor’s graduates. Provides customer-facing design services, technical sales support, and troubleshooting for Cadence EDA tools. The one-year program includes rotations across digital, physical, analog, package, systems, verification, and emulation design, with training in HDLs, synthesis, UNIX, programming, scripting, and silicon analysis. Graduates transition into a permanent CST business group based on interests and company needs.

Leads front-end semiconductor design projects and mentors RTL engineers. Defines microarchitecture, develops and optimizes RTL in Verilog, SystemVerilog, or VHDL, and oversees pre-silicon verification, lint, CDC, formal verification, synthesis, and signoff. Collaborates with design verification, physical design, architecture, and firmware teams to deliver IPs and SoCs meeting PPA goals. Supports SDC creation, physical design, and static timing analysis teams.

Leads physical design and DFT teams delivering advanced-node SoCs from RTL or netlist through GDS. Owns customer engagements, technical decisions, PPA optimization, timing and power closure, foundry and library selection, sign-off criteria, and schedule execution. Collaborates with RTL, synthesis, CAD, library, tools R&D, and customer teams while improving methodologies, AI adoption, and best practices. Requires deep expertise in digital implementation flows, backend EDA tools, advanced semiconductor nodes, scripting, and customer-facing technical leadership.

Leads cross-functional teams delivering semiconductor services projects and technology initiatives from scoping through completion. Responsibilities include creating statements of work and cost plans, managing schedules, budgets, risks, resources, deliverables, customer communications, and commercial negotiations. The role partners with account, technical, finance, legal, sales, field, and services teams while driving customer satisfaction and process improvements. Occasional domestic and international travel is required.

Leads semiconductor design verification strategy and execution using UVM/SystemVerilog, constrained-random testing, formal verification, and gate-level simulation. Designs reusable testbenches, develops complex sequences, analyzes coverage, debugs design issues, and oversees verification sign-off. Mentors junior engineers, coordinates with design, architecture, and emulation teams, and manages verification schedules, risks, and priorities.

Lead design verification strategy and execution for customer ASIC projects. Architect reusable UVM/SystemVerilog testbenches, develop constrained-random tests, analyze coverage, perform formal verification and gate-level simulation, debug complex design issues, and provide verification sign-off. Mentor junior engineers, manage verification schedules and risks, and collaborate with design, architecture, emulation, and customers.

Lead verification strategy and architecture for semiconductor ASIC and SoC designs. Build reusable UVM/SystemVerilog testbenches, develop constrained-random tests, perform formal verification and gate-level simulation, analyze coverage, debug complex design issues, and approve verification sign-off. Mentor junior engineers, coordinate with design, architecture, and emulation teams, and manage verification schedules, risks, and priorities.

Leads design verification strategy and architecture for customer ASIC projects. Designs reusable UVM/SystemVerilog testbenches, develops constrained-random tests, manages coverage, performs formal verification and gate-level simulation, and debugs complex design issues. Provides technical leadership through customer interaction, sign-off approval, cross-functional collaboration, project scheduling, risk management, and mentorship of junior engineers.

Lead functional verification for Cadence memory controller IP. Develop and enhance UVM-based verification environments, create test plans, validate customer configurations through regression testing, analyze functional and code coverage, support customers using the environment, and ensure designs meet technical and quality requirements.

Architects and designs processor core logic enhancements in partnership with the Chief Architect. Collaborates with validation and physical design teams to productize solutions, focusing on areas such as load/store, instruction fetch, branch prediction, memory management, and bus protocols. The role may also analyze performance bottlenecks, model improvements, and implement optimization solutions.

Supports Cadence digital implementation and signoff products by debugging customer issues, partnering with R&D and release teams, running design benchmarks, and developing implementation flows. Requires deep expertise in ASIC RTL-to-GDSII methodologies, timing closure, PPA optimization, physical design, low-power and hierarchical design, and industry-standard EDA tools. The role also involves automation using Perl, Tcl, and shell scripting.

Support Cadence Conformal products, especially equivalency checking, by troubleshooting customer issues, debugging systematically, identifying workarounds, and translating findings for R&D. Collaborate with customers and R&D on product features, enhancements, and solutions. Apply RTL synthesis and verification knowledge, scripting skills in Tcl and Perl, technical writing, and strong communication to meet deadlines and resolve ambiguous problems.

Leads a processor design verification team responsible for verifying microprocessor cores and peripherals. Develops verification plans, simulation and emulation testbenches, diagnostics, assertions, coverage monitors, and automated verification flows. Drives coverage closure, collaborates with design, architecture, firmware, and verification teams, and manages work reporting for 7–10 engineers. Requires deep CPU architecture, SystemVerilog, UVM, gate-level simulation, assembly programming, and design verification leadership experience.

Lead architecture, development, and execution for Conformal logical equivalence checking and ECO technologies. Drive formal verification, scalability, performance, quality, debugging, and AI-powered innovation. Guide complex technical initiatives, resolve customer escalations, influence product strategy, collaborate across engineering and product teams, mentor senior engineers, and engage strategic semiconductor customers and partners.

Build and manage sales pipelines for Design IP technology across North American accounts. Drive market penetration, adoption, revenue, and strategic sales plans while managing complex $1M+ licensing deals. Collaborate with engineering, marketing, legal, finance, executives, and EDA sales teams. Develop customer relationships from startups to enterprises, articulate IP value propositions, negotiate contracts, meet revenue targets, and provide market feedback to product leadership.

Lead digital design engineer responsible for designing and integrating SoC IPs, developing microarchitectural specifications, performing lint, CDC, synthesis, and PPA optimization, and supporting verification and physical design teams. The role also involves creating synthesis constraints, debugging design issues, automating repetitive tasks with scripting, and collaborating across engineering teams.

Design and integrate SoC IPs from architectural specifications; perform Lint and CDC checks; develop synthesis constraints and optimize power, performance, and area. Create microarchitectural specifications, support verification and physical design teams, and automate repetitive tasks using scripting. Collaborate across teams to execute projects effectively.

Develop bare-metal firmware in C for DDR5 PHY using microcontrollers; implement low-level APIs and training algorithms; collaborate with hardware designers and verification teams for firmware-hardware co-verification; debug in RTL (C+Verilog) simulations and on silicon bring-up; use scripting and EDA tools for verification and diagnostics.

Lead verification projects at subsystem/SOC level, develop testbenches, mentor engineers, and ensure metric-driven quality verification processes.

The role involves collaborating with R&D and Application Engineering teams to enhance chip design tools, focusing on PPA benchmarking and optimization.