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NVIDIA

ASIC Design Engineer, Tools and Methodology Development

Posted 10 Days Ago
Be an Early Applicant
Hybrid
Austin, TX, USA
116K-219K Annually
Mid level
Hybrid
Austin, TX, USA
116K-219K Annually
Mid level
Develop and deploy internal ASIC design tools, RTL generation workflows, verification utilities, and methodologies across NVIDIA engineering teams. Maintain DevOps-style automated RTL generation operations, support reusable design blocks, and integrate workflows into IP development environments. Requires digital design and Verilog expertise, Python or Perl scripting, Unix/Linux shell scripting, and Makefiles. Experience with ASIC verification, clocks/resets, CDC flows, synthesis, and timing is advantageous.
The summary above was generated by AI

NVIDIA is looking for an ASIC Design Engineer with proven hardware design and methodology expertise to join our world-class team to help amplify human creativity and intelligence.
 

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing! More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to pursue, that only we can seek, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today!
 

What you'll be doing:

  • Develop and deploy in-house tools and workflows to support engineering business units across NVIDIA.

  • Take ownership of tools that verify common design blocks used in all products at NVIDIA.

  • Act as a "DevOps" engineer for automated RTL generation by developing new features and maintaining efficient operations for existing users.

  • Build new workflows and methodologies to ensure smooth integration into various IP development environments.
     

What we need to see:

  • Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering (or equivalent experience).

  • 3+ years of proven experience preferred.

  • Solid understanding of fundamental digital design concepts with hands-on experience in Verilog.

  • Proficiency in scripting using modern Python and/or Perl.

  • Experience with Unix/Linux shell scripting and Makefiles.

  • Strong ability to collaborate with multi-functional teams and effectively communicate technical details.

Ways to stand out from the crowd:

  • Prior experience in ASIC verification.

  • Knowledge of Clocks/Resets design and verification.

  • Exposure to CDC related design/verification flows.

  • Exposure to backend flows (Synthesis, Timing, etc).

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of constant innovation and creating the highest performance products in the industry? If so, we want to hear from you.

#LI-Hybrid

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until September 12, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

NVIDIA Austin, Texas, USA Office

Austin, United States

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