Cisco Logo

Cisco

ASIC Physical Design Engineer

Posted 2 Days Ago
Be an Early Applicant
In-Office or Remote
2 Locations
138K-256K Annually
Senior level
In-Office or Remote
2 Locations
138K-256K Annually
Senior level
Design and optimize advanced ASIC physical implementations from RTL through GDSII. Responsibilities include floorplanning, placement and routing, clock tree synthesis, static timing analysis, power integrity, equivalence checks, timing ECOs, signoff, and methodology automation. The engineer collaborates with RTL, DFT, implementation, EDA vendor, and tool-flow teams to improve performance, die size, timing closure, and design efficiency across advanced process technologies.
The summary above was generated by AI
The application window is expected to close on: 10/29/2026Meet the Team

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms powering Cisco’s core Switching, Routing, and Wireless products. We design networking hardware for enterprises, service providers, the public sector, and nonprofit organizations worldwide. As part of the team behind Cisco Silicon One—the industry’s only unified silicon architecture spanning top-of-rack switches to web-scale data centers—you’ll help shape Cisco’s groundbreaking solutions by designing, developing, and testing some of the most advanced ASICs in the industry.


Your Impact
  • RTL-to-GDSII implementation, including hierarchical floorplanning, place and route, static timing analysis, power integrity, and equivalence checks with a focus on performance and die size optimization.
  • Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements.
  • Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology.
  • Guide clock tree synthesis (CTS) strategies and provide actionable feedback to the implementation teams.
  • Execute STA setup, convergence methodologies, and sign-off processes across multi-mode, multi-corner scenarios.
  • Complete Timing ECO implementation using Tweaker/Primetime-based flows and contribute to automation for STA methodology.
  • Evaluate multiple timing methodologies/tools across different technologies and design types.


Minimum Qualifications
  • Bachelor’s Degree in Electrical Engineering with 6+ years of Physical Design experience or Master’s Degree in Electrical Engineering with 4+ years of Physical Design experience, or PhD in Electrical Engineering with 2+ years of Physical Design experience.
  • Experience with RTL2GDSII flow and design tapeouts in 7nnm/5nm/3nm or below process technologies.
  • Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre.


Preferred Qualifications
  • Experience with hierarchical design, timing closure, physical convergence, and power integrity analysis.
  • Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
  • Experience with Python, TCL, or Perl programming.
Why Cisco? 

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. 

We are Cisco, and our power starts with you. 

Message to applicants applying to work in the U.S. and/or Canada:The starting salary range posted for this position is $167,700.00 to $245,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks.  Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

  • 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees

  • 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco

  • Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees

  • Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)

  • 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next

  • Additional paid time away may be requested to deal with critical or emergency issues for family members

  • Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:

  • .75% of incentive target for each 1% of revenue attainment up to 50% of quota;

  • 1.5% of incentive target for each 1% of attainment between 50% and 75%;

  • 1% of incentive target for each 1% of attainment between 75% and 100%; and

  • Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area:

$155,000.00 - $256,000.00

Non-Metro New York state & Washington state:

$138,100.00 - $227,900.00

* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

Similar Jobs

One Month Ago
Remote
United States
190K-280K Annually
Expert/Leader
190K-280K Annually
Expert/Leader
Defense • Manufacturing
Lead end-to-end RTL-to-GDSII physical design for high-performance SoCs in advanced FinFET nodes. Own synthesis, floorplanning, P&R, CTS, STA, DRC/LVS and sign-off; develop methodologies and automation to optimize PPA; drive timing closure, coordinate package/SI/PI and DFT, manage external PD partners and EDA tool flows, and support post-silicon bring-up and production for spaceflight-qualified designs.
Top Skills: 2.5D/3D Advanced PackagingCadenceClock Tree Synthesis (Cts)CpfDftDrcEco ImplementationFinfetGate-All-AroundGdsiiIr Drop AnalysisLvsMixed-Signal SocsRtlRtl-To-GdsiiSi/PiSiemens EdaStatic Timing Analysis (Sta)SynopsysTapeoutTsmcUpf
One Month Ago
Remote
United States
170K-250K Annually
Senior level
170K-250K Annually
Senior level
Defense • Manufacturing
Lead full physical design flow for complex SoC blocks and top-level integration from synthesis to GDSII. Drive timing closure, PPA optimization, physical sign-off (DRC/LVS, IR drop, EM), ECOs and tapeout. Collaborate with front-end, verification, DFT, packaging teams and external vendors, develop automation and methodology, and support products through production and spaceflight.
Top Skills: 2.5D Packaging3D PackagingCadence InnovusChip-Package Co-DesignCpfCtsDftDrcEco ImplementationEm AnalysisFinfetFloorplanningFusion CompilerGate-All-AroundGdsiiIr Drop AnalysisLvsPhysical VerificationPlace And RouteScripting/AutomationStaSynopsys Icc2SynthesisTsmc Sign-OffUpf
An Hour Ago
Remote
USA
223K-279K Annually
Senior level
223K-279K Annually
Senior level
Consumer Web • Healthtech • Professional Services • Social Impact • Software
Own the Supervisory Billing product end to end, including strategy, roadmap, revenue growth, state and payer expansion, operational scaling, and new product development. Lead cross-functional initiatives to expand the addressable market, improve efficiency for thousands of customers and appointments, and launch concepts such as a supervisor-supervisee marketplace.

What you need to know about the Austin Tech Scene

Austin has a diverse and thriving tech ecosystem thanks to home-grown companies like Dell and major campuses for IBM, AMD and Apple. The state’s flagship university, the University of Texas at Austin, is known for its engineering school, and the city is known for its annual South by Southwest tech and media conference. Austin’s tech scene spans many verticals, but it’s particularly known for hardware, including semiconductors, as well as AI, biotechnology and cloud computing. And its food and music scene, low taxes and favorable climate has made the city a destination for tech workers from across the country.

Key Facts About Austin Tech

  • Number of Tech Workers: 180,500; 13.7% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Dell, IBM, AMD, Apple, Alphabet
  • Key Industries: Artificial intelligence, hardware, cloud computing, software, healthtech
  • Funding Landscape: $4.5 billion in VC funding in 2024 (Pitchbook)
  • Notable Investors: Live Oak Ventures, Austin Ventures, Hinge Capital, Gigafund, KdT Ventures, Next Coast Ventures, Silverton Partners
  • Research Centers and Universities: University of Texas, Southwestern University, Texas State University, Center for Complex Quantum Systems, Oden Institute for Computational Engineering and Sciences, Texas Advanced Computing Center

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account