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NVIDIA

ASIC Verification Engineer

Reposted 8 Days Ago
Be an Early Applicant
In-Office
Austin, TX, USA
116K-190K Annually
Mid level
In-Office
Austin, TX, USA
116K-190K Annually
Mid level
The ASIC Verification Engineer will develop and automate verification test plans, ensuring code coverage and collaborating with teams on design verification processes. This role requires strong analytical and debugging skills with experience in RTL verification methodologies.
The summary above was generated by AI

NVIDIA is looking for a ASIC Verification Engineer to help verify our global IP! This position offers an opportunity to impact an array of products while collaborating with teams from design, architecture, verification, and integration.
 

At NVIDIA, we have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. In this position, you will partner with the design and architecture teams to help make the right implementation choices, craft and implement verification test plans, maintain regressions, close coverage and sign off design or both functional correctness and for meeting performance expectations. This position offers the opportunity to have a real impact on multiple product lines including consumer graphics, self-driving cars, HPC, cloud computing, and AI!
 

What you'll be doing:

  • Develop test plans, tests and verification infrastructure for verifying global IP across multiple products

  • Define, develop, and automate flows and methodologies to efficiently build, deploy, and verify generated RTL

  • Ensure code and functional coverage of all the RTL which you will verify

  • Build verification components using SV/UVM methodology

  • Driving coverage-based verification closure

  • Collaborate with design teams across NVIDIA to find corner cases and resolve verification related issues
     

What we need to see:

  • BS/MS in Electrical or Computer Engineering (or equivalent experience)

  • 2+ years of proven design verification experience

  • Experience in pre-silicon verification (UVM, SystemVerilog), ASIC design/implementation flow, and design automation

  • Programming and scripting experience in Perl or Python

  • Excellent debugging and analytical skills

  • Exposure to design and verification tools (dc_shell or equivalent synthesis tools, VCS or equivalent simulation tools, debug tools like Debussy, GDB)

  • Strong communication and collaboration skills to interact within the team and across functional teams

Ways to stand out from the crowd:

  • Previous experience automating tasks in the design verification process

  • Hands on experience in object-oriented programming

  • Prior design or verification experience at the IP or block level

  • Experience developing methodologies used by others

  • Demonstrated ability to drive a project to completion

NVIDIA is widely considered to be one of the technology world’s most desirable employers! We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you.
 

#LI-Hybrid

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 116,000 USD - 189,750 USD.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until April 19, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Top Skills

Dc_Shell
Debussy
Gdb
Perl
Python
Systemverilog
Uvm
Vcs

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