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Cadence Design Systems

Design Engineering Director

Posted Yesterday
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In-Office
Austin, TX, USA
Expert/Leader
In-Office
Austin, TX, USA
Expert/Leader
Lead front-end semiconductor design projects and mentor RTL engineers. Define microarchitecture, develop and optimize RTL in Verilog, SystemVerilog, or VHDL, and oversee verification and signoff activities including lint, CDC, and formal verification. Collaborate with design verification, physical design, architecture, and firmware teams. Support synthesis, SDC creation, physical design, and static timing analysis while delivering IP and SoC integrations against performance, power, and area goals.
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Solutions (North America) team is looking for an experienced candidate to lead Front End Design projects. This is a challenging and rewarding opportunity is for a highly motivated engineer with a passion for innovation and a proven track record of success in the semiconductor industry.

This is a leadership role where you will be responsible for:

Technical Leadership:

Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment.

Design & Microarchitecture:

Define and develop microarchitectural features for IPs and subsystems, ensuring they meet PPA goals.

RTL Development:

Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL to create complex digital logic.

Verification & Signoff:

Oversee pre-silicon verification activities, including Lint, Clock Domain Crossing (CDC), Formal Verification (FV), and other quality checks.

Collaboration:

Work closely with cross-functional teams, including Design Verification (DV), Physical Design (PD), Architecture, and firmware engineers, to ensure successful delivery.

Qualifications:

*10+ years of Front End design and/or verification with a BS/MS Engineering or Computer Sciences

*Proven experience in leading and managing complex engineering projects

*Rich experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration

*Expert in RTL design (Verilog), simulators debuggers

*Hands on Experience in Synthesis, SDC creation and support PD and STA teams.

*Experience in driving results in multi-disciplinary organization

Desirable:

A Self-motivated person with good communication and design management skills 

Experience with Cadence front end toolset

We’re doing work that matters. Help us solve what others can’t.

We’re doing work that matters. Help us solve what others can’t.

Cadence Design Systems Austin, Texas, USA Office

Austin, United States

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