Tenstorrent Inc. Logo

Tenstorrent Inc.

DFT Engineer

Posted 4 Days Ago
Be an Early Applicant
Remote
Hiring Remotely in United States
100K-500K Annually
Expert/Leader
Remote
Hiring Remotely in United States
100K-500K Annually
Expert/Leader
Design and implement chip-level DFT strategies for high-speed CPU cores and multi-chiplet SiP. Implement and verify scan chains, memory BIST, and JTAG. Partner with RTL, physical design, and verification teams. Script and automate DFT flows using EDA tools (ATPG, fault coverage) and support SoC-level silicon debug, formal verification, and DFT signoff.
The summary above was generated by AI

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent is looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. In this role, you will be responsible for DFT implementation using industry standard tools for high-speed CPU core design. 

This role is remote based out of the United States.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.


Who you are

  • You have a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or Computer Science, along with 10+ years of relevant DFT experience.
  • You have hands-on experience with industry-standard DFT tools such as Synopsys and Siemens, as well as scripting in TCL and Python.
  • You bring expertise in DFT planning, SoC-level silicon debug, formal verification, and signoff of inserted DFT logic.
  • You are a strong cross-functional collaborator who can assess risk, communicate resource needs, and deliver in a complex technical environment.

What we need

  • Build and execute chip-level DFT strategies for high-speed CPU core designs and multi-chiplet System-in-Package programs.
  • Implement and verify DFT features including scan chains, memory BIST, and JTAG to support manufacturing test and silicon debug.
  • Partner with RTL, physical design, and verification teams to ensure testability throughout the design flow.
  • Script, automate, and analyze DFT flows using industry-standard EDA tools, including ATPG and fault coverage reporting.

What you will learn

  • How to develop DFT strategies for advanced multi-chiplet and System-in-Package designs.
  • How Tenstorrent approaches testability, silicon bring-up, and manufacturing readiness for high-performance CPU programs.
  • How to work across global teams and external stakeholders on complex silicon development efforts.
  • How to scale DFT execution through automation, deeper cross-functional collaboration, and continuous IP improvement.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.  Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).   These requirements apply to persons located in the U.S. and all countries outside the U.S.  As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.  If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Similar Jobs

9 Days Ago
Remote
Arizona, USA
Senior level
Senior level
Cloud • Enterprise Web • Hardware • Information Technology • Internet of Things • Robotics • Semiconductor
Design-for-test (DFT) implementation and validation for 3nm/5nm networking SoCs and IPs. Perform RTL checks, scan-insertion, ATPG pattern generation (compressed/uncompressed), pattern simulation, MBIST and JTAG insertion/verification, silicon debug, and automation/scripting to enhance DFT flows.
Top Skills: AtpgCadence ModusDaertIeee 1149.1 JtagMakefileMbistMentor TessentPattern SimulationPerlScan InsertionShellSynopsys SpyglassSynopsys TetramaxTclTessent TestkompressVcsVerdi
9 Days Ago
In-Office or Remote
CA, USA
160K-300K Annually
Expert/Leader
160K-300K Annually
Expert/Leader
Artificial Intelligence • Hardware • Healthtech • Machine Learning • Wearables
Lead full-chip DFT architecture and implementation including scan, compression, MBIST/BIST, ATPG vector generation, gate-level verification, and silicon debug. Collaborate with STA, physical design, memory compiler, and test teams to ensure production-ready silicon with high test coverage and diagnostic capability, and support bring-up and debug on silicon.
Top Skills: AtpgBistBoundary ScanCadence GenusCadence ModusCompression LogicGate-Level SimulationJtagMbistMemory CompilerScan ChainsSilicon DebugTcl
9 Days Ago
Remote
California, USA
Senior level
Senior level
Cloud • Enterprise Web • Hardware • Information Technology • Internet of Things • Robotics • Semiconductor
Design and implement DFT (scan, MBIST, ATPG), verify test patterns via gate‑level simulations, perform post‑silicon diagnosis, and collaborate with synthesis, STA, physical design, and test engineers to debug DFT issues and bring up test vectors on silicon. Automate flows using TCL and use Tessent/Synopsys tools for implementation and verification.
Top Skills: AtpgGate-Level SimulationJtagMbistPhysical DesignPost-Si DiagnosisScanSiemens-TessentStaSynopsysSynthesisTclVector Generation

What you need to know about the Austin Tech Scene

Austin has a diverse and thriving tech ecosystem thanks to home-grown companies like Dell and major campuses for IBM, AMD and Apple. The state’s flagship university, the University of Texas at Austin, is known for its engineering school, and the city is known for its annual South by Southwest tech and media conference. Austin’s tech scene spans many verticals, but it’s particularly known for hardware, including semiconductors, as well as AI, biotechnology and cloud computing. And its food and music scene, low taxes and favorable climate has made the city a destination for tech workers from across the country.

Key Facts About Austin Tech

  • Number of Tech Workers: 180,500; 13.7% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Dell, IBM, AMD, Apple, Alphabet
  • Key Industries: Artificial intelligence, hardware, cloud computing, software, healthtech
  • Funding Landscape: $4.5 billion in VC funding in 2024 (Pitchbook)
  • Notable Investors: Live Oak Ventures, Austin Ventures, Hinge Capital, Gigafund, KdT Ventures, Next Coast Ventures, Silverton Partners
  • Research Centers and Universities: University of Texas, Southwestern University, Texas State University, Center for Complex Quantum Systems, Oden Institute for Computational Engineering and Sciences, Texas Advanced Computing Center

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account