Physical Design Engineer (AS-64000921)

Responsibilities:

• We will incorporate you on a team that is involved in all aspects of physical implementation from RTL to GDSII.
• Perform RTL synthesis and scan stitching.
• Apply deep knowledge of timing optimization and experience with ECO generation to analyze and fix timing issues in 40nm, 28nm and below.
• You will be defining and debugging Timing Constraints and performing STA using industry-standard STA engines and a deep understanding of timing correlation to achieve timing closure.
• Build timing constraints for the entire chip in a team environment.
• Knowledge of automating and advancing flows using proficiency in Perl/Tcl scripting.
• Analyze power constraints and chip floor plan.
• You will analyze clock distribution on full-chip assembly.
• Physical design-related flow development, tool evaluation, flow automation, QA and improvement.
• You will develop Placement & Route structures for a complete ASIC design.
• Build Static Timing Analysis, timing closure, ECO and tape-out.
• IR Drop analysis and improvement on almost all designs

Required Skills and Qualifications:

• Bachelor's or Master's in Electrical Engineering and 3+ years of industry experience in a Logic design or Physical Design position.
• Strong solid understanding of RTL design, and the ideal candidate should be familiar with Cadence Genus/Innovus and Synopsys Design Compiler/ICC/Fusion Compiler
• Experience with Primetime, Conformal LEC, and ATPG.
• Solid understanding of scan insertion and ATPG.
• Good communication and collaboration skills.

Preferred Skills and Qualifications:

• Ability to be involved in design/architecture reviews which will help add to the overall progress and improvement of the team.
• Define physical design methodologies and flow automation.
• Ability to perform debug/analysis skills for designs, library, and technology files.
• Ability to provide mentorship and guidance to junior engineers and be a very effective teammate.