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Ambiq Micro

Sr. Staff Engineer - Timing Methodology

Posted 2 Days Ago
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In-Office
Austin, TX
Senior level
Easy Apply
In-Office
Austin, TX
Senior level
Lead timing methodology and closure for block and SoC levels in modern FinFET/multi-patterning processes. Define flows, constraints, signoff correlation, timing margining, glitch noise analysis, and collaborate with RTL, PnR, DFT, and post-silicon teams to achieve timing convergence and best-in-class PPA.
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Company Overview 

Ambiq's mission is to enable intelligence everywhere by delivering the lowest power semiconductor solutions. Ambiq is a pioneer and a leading provider of ultra-low-power semiconductor solutions based on our proprietary and patented sub- and near-threshold technologies. With the increasing power requirements of artificial intelligence (AI) computing, our customers are relying on our solutions to deliver AI to edge environments. Our hardware and software innovations fundamentally deliver a multi-fold improvement in power consumption over traditional semiconductor designs without expensive process geometry scaling. We began in 2010 by addressing the power consumption challenges of battery-powered devices at the edge, where they were most pronounced. As of the beginning of 2025, we've shipped more than 280+ million units worldwide. 

Our innovative and fast-moving teams of design, research, development, production, marketing, sales, and operations are spread across several continents, including the US (Austin), Taiwan (Hsinchu), China (Shanghai and Shenzhen), and Singapore. We value relentless technology innovation, a deep commitment to customer success, collaborative problem-solving, and an enthusiastic pursuit of energy efficiency. We embrace candidates who also share these same values. The successful candidate must be self-motivated, creative, and comfortable learning and driving exciting new technologies. We encourage and nurture an environment that fosters growth and opportunities to work on complex, meaningful, and challenging projects, creating a lasting impact and shaping the future of technology. Join us on our quest for enabling billions of intelligent devices. The intelligence everywhere revolution starts here. 

Scope 

As a Sr. Staff Engineer - Timing Methodology, you will play a critical role in transforming our cutting-edge designs into silicon reality. You will be responsible for all aspects of timing closure from defining methodology, developing flows, closing timing at the block level and timing convergence at SOC level as well.

Responsibilities:
  • In-depth expertise on Timing Methodology and Timing closure both at block level and SOC level in modern Finfet and multi-patterning based process technologies using Cadence Tempus or Synopsys Primetime.
  • Own all aspects of timing convergence, including Signoff to build timing correlation, PVTRc corner definition, timing      margining, extraction, signoff timing analysis, glitch noise analysis, timing ECOs and interplay and tradeoff with power. 
  • Own, define and drive constraints in collaboration with RTL and IP Vendors.Have in-depth understanding of all timing collaterals for different type of  Ips, namely, hard IP, Stdcell and Memory etc.
  • Partner with post-si bringup and testing to ensure pre-si timing correlates well to post-si.
  • Collaborate closely with RTL designers, DFT and other stakeholders to achieve best in class PPA. 
  • Continuously improve timing analysis methodologies and scripts to enhance efficiency and flow consistency. Stay at the forefront of  advancements in STA  and new process nodes
Requirements
  • Master's degree in Electrical Engineering or Computer Engineering (or a related field)
  • Minimum of 8 years of experience in Timing Analysis and convergence.
  • Proven expertise in static timing analysis using industry-standard timing tools like Primetime (Synopsys) or Tempus (Cadence).
  • In-depth understanding of digital circuit design principles and concepts
  • Strong proficiency with industry-standard EDA tools (e.g., Synopsys, Cadence)
  • Excellent analytical and problem-solving skills
  • Ability to work effectively in a team environment and communicate complex technical concepts clearly
  • Experience with scripting languages (e.g., TCL, Python)
  • Experience with PnR tools like Fusion Compiler (Synopsys) and Innovus (Cadence) is a plus.

Must be currently authorized to work in the United States for any employer. We do not sponsor or take over sponsorship of employment visas (now or in the future) for this role.

What You Need 

We're seeking passionate technologists who thrive on pushing boundaries, solving complex challenges, and driving transformative solutions. 

At Ambiqyou'll collaborate with a dynamic team that values relentless innovation, customer-centric thinking, and continuous learning. If you're a self-motivated, creative problem-solver eager to push technological limits and make a meaningful impact in energy efficiency, this is your opportunity to grow, excel, and turn groundbreaking ideas into reality. 

Most importantly, the successful candidate will be able to live the Ambiq Shared Values: 

  • Innovate: We tenaciously find ways to break down the barriers to possible solutions 
  • Collaborate: We proactively communicate and encourage each other to be better. 
  • Focus: We keep the voice of the customer at the center of everything we do. 
  • Learn: We strive for continuous improvement and are always curious. 
  • Achieve: We execute on quality and follow through on our commitments. 

Top Skills

Cadence Tempus,Synopsys Primetime,Synopsys,Cadence,Fusion Compiler,Innovus,Tcl,Python,Finfet,Multi-Patterning,Sta (Static Timing Analysis)

Ambiq Micro Austin, Texas, USA Office

Austin, TX, United States

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